Patents by Inventor Masashige Mizuyama

Masashige Mizuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8489862
    Abstract: An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: July 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Masahiko Saito, Masashige Mizuyama
  • Patent number: 7831973
    Abstract: Each task #1, #2 registers signal handlers belonging thereto in a signal-handler table through a handler registering section in an OS, and registers itself and the priority thereof in a task/handler priority table through a task registering section. When a signal is generated, a signal notifying section specifies a signal handler corresponding to the signal and the priority thereof by referring to the signal-handler table, and a task/handler selecting section selects a task or signal handler having a highest priority in the task/handler priority table. A task executing section executes the selected task and a signal-handler executing section executes the selected signal handler.
    Type: Grant
    Filed: December 24, 2004
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Katsushige Amano, Masashige Mizuyama
  • Publication number: 20100185833
    Abstract: An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.
    Type: Application
    Filed: June 5, 2008
    Publication date: July 22, 2010
    Inventors: Masahiko Saito, Masashige Mizuyama
  • Publication number: 20080307248
    Abstract: A program execution time determining portion determines an execution start time and a processing volume per unit time of a program in such a manner that a processing volume necessary to execute the program is made equal to the extent that registered request for the execution time and allowable range are met. It is thus possible to determine the execution time of the program in such a manner that a necessary processing volume is made as equal as possible within the allowable range of the request for the execution time of the program, which enables clock control that suppresses a variation of the operating frequency of the CPU. Power consumption of the CPU can be thus reduced.
    Type: Application
    Filed: April 20, 2005
    Publication date: December 11, 2008
    Inventors: Katsushige Amano, Masashige Mizuyama
  • Patent number: 7346791
    Abstract: A clock controller controls a clock generated by a clock generator to determine a clock frequency. A computing device executes software obtained from a storage in accordance with the clock supplied via the clock controller. An exclusive processing section detector detects the start and end of an exclusive processing section which is a section during which an exclusive processing is executed. A clock control judging device commands the clock controller to decrease the clock frequency if the exclusive processing section detector has detected the start of a specific processing section, while commanding the clock controller to decrease the clock frequency if the exclusive processing section detector has detected the end of the specific processing section.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: March 18, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuomi Kato, Masashige Mizuyama
  • Patent number: 7246126
    Abstract: A terminal-side communications control unit makes a request to a server for retrieving an instruction file that describes an instruction for transmitting transmission data. The server transmits the instruction file in response to the request for retrieving the instruction file. On receiving the instruction file, the terminal-side communications control unit causes an application executing unit to execute an application, and also forwards the instruction file to a transmission data generating unit. On receiving the instruction file, the transmission data generating part refers to the instruction file to generate, from generated data stored in a generated data storage unit, transmission data to be transmitted to the server.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: July 17, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Inami, Takako Hirose, Masashige Mizuyama, Atsunobu Kato, Munehito Matsuda, Hidehiko Shin, Hiromi Wada
  • Publication number: 20060195847
    Abstract: A high priority setter 102 writes the first priority (high priority) of a specific task #1 recorded in a specific task table 110 every time interval T, as the priority of the task #1 in a task priority table 111. Thereafter, when a time duration TH shorter than the time interval T elapsed, a low priority setter 103 writes the second priority (low priority) of the specific task #1 recorded in the specific task table 110, as the priority of the task #1 in the task priority table 111. The second priority is set lower than the first priority. A task selector 101 selects a task whose priority is set the highest among the tasks 10 recorded in the task priority table 111, as a specific task to be executed.
    Type: Application
    Filed: December 3, 2004
    Publication date: August 31, 2006
    Inventors: Katsushige Amano, Masashige Mizuyama
  • Publication number: 20060161922
    Abstract: Each task #1, #2 registers signal handlers belonging thereto in a signal-handler table 112 through a handler registering section 111 in an OS 100, and registers itself and the priority thereof in a task/handler priority table 101 through a task registering section. When a signal is generated, a signal notifying section 131 specifies a signal handler corresponding to the signal and the priority thereof by referring to the signal-handler table 112, and a task/handler selecting section 141 selects a task or signal handler having a highest priority in the task/handler priority table 101. A task executing section 150 executes the selected task and a signal-handler executing section 151 executes the selected signal handler.
    Type: Application
    Filed: December 24, 2004
    Publication date: July 20, 2006
    Inventors: Katsushige Amano, Masashige Mizuyama
  • Patent number: 6920481
    Abstract: In a communications terminal 3, a CPU 32 retrieves start-up data 112 from a server 1 using a Web browser 311, which is stored in a storage device 31. The CPU 32 performs data authentication with respect to authentication type data 1123 included in the start-up data 112. Then, when the authentication is succeeded, the CPU 32 follows the authentication type data 1123 so as to determine which authentication mode is to be used for authenticating the application data. In this manner, the authentication mode for authenticating the application data can be easily changed.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: July 19, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Inami, Masashige Mizuyama, Atsunobu Kato
  • Publication number: 20050144408
    Abstract: A memory protection unit, a memory protection method and a computer-readable record medium in which a memory protection program is recorded is provided which are capable of preventing a memory from being improperly rewritten by a malfunction in a subroutine. This memory protection unit includes: a memory which has at least one memory area that is used by at least one subroutine, and in which a writing attribute that shows a writing permission or a writing prohibition can be set for every memory area; a subroutine choice section which chooses a subroutine that executes a processing request; a memory-area specification section which specifies a memory area that is used by the subroutine; and a subroutine calling section which sets, to the writing permission, the writing attribute of the specified memory area, calls the chosen subroutine, and sets, to the writing prohibition, the writing attribute of the memory area after completing the execution of the subroutine.
    Type: Application
    Filed: December 27, 2004
    Publication date: June 30, 2005
    Inventors: Kenji Ejima, Masashige Mizuyama
  • Publication number: 20040193935
    Abstract: A clock controller 102 controls a clock generated by a clock generator 101 to determine a clock frequency. A computing device 103 executes a software obtained from a storage 104 in accordance with the clock supplied via the clock controller 102. An exclusive processing section detector 110 detects the start and end of an exclusive processing section which is a section during which an exclusive processing is executed. A clock control judging device 111 commands the clock controller 102 to decrease the clock frequency if the exclusive processing section detector 110 has detected the start of a specific processing section, while commanding the clock controller 102 to decrease the clock frequency if the exclusive processing section detector 110 has detected the end of the specific processing section.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 30, 2004
    Inventors: Kazuomi Kato, Masashige Mizuyama
  • Publication number: 20030217246
    Abstract: The present invention provides a memory control apparatus capable of efficiently reducing power consumption. The memory control apparatus controls power consumption for refreshing on a unit region-by-unit region basis. A determination section 22 receives an allocate request from an application and determines whether or not data requires refreshing based on the allocate request. Next, a memory allocating section 23 allocates a memory region within a first memory bank to data having been determined to require refreshing and allocates amemory region within a second memory bank to data having been determined to require no refreshing. A memory control section 25 specifies the first memory bank as a refresh region for refreshing and specifies the second memory region as a non-refresh region which is prevented from being refreshed.
    Type: Application
    Filed: May 15, 2003
    Publication date: November 20, 2003
    Inventors: Kenichi Kubota, Hiroyuki Waki, Junichiro Soeda, Masashige Mizuyama
  • Publication number: 20030177191
    Abstract: An information processor that can exchange information in real time between particular users by using an email system, and that can display a mail message received from a non-particular user even when the information is being exchanged. The information processor 1 includes a mail message sending section 101 for sending the mail message, a mail message receiving section 102 for receiving the mail message, a display section 104 for displaying the mail message, and a control section 105 for controlling switching between a particular mail message display mode and a non-particular mail message display mode. When returning to the particular mail message display mode after switching to the non-particular mail message display mode from the particular mail message display mode, the control section 105 causes the display section 104 to redisplay the contents displayed at the time of switching.
    Type: Application
    Filed: February 25, 2003
    Publication date: September 18, 2003
    Inventors: Takashi Kawashima, Hideaki Fukushima, Masashige Mizuyama, Hiromi Wada, Takuya Kobayashi, Atsunobu Kato
  • Publication number: 20020116633
    Abstract: Command data 111 includes an address of terminal data 112 to be received. A data processor 100 first verifies a signature applied to the received command data 111, and then receives the terminal data 112 specified by the command data 111. Thus received terminal data is used for controlling the data processor 100 such as screen display. At this time, the received data may be segmented into a protected data region and an unprotected data region, and any data type included in the unprotected data region may be listed as an unprotection list. If listed, the unprotection list may be arranged in the protected data region. Alternatively, a signer certificate may indicate, by type, what data is signable by its signer, and at the time of data reception, determination may be made whether the signer has an authorization for signing the data classified under the type.
    Type: Application
    Filed: January 17, 2002
    Publication date: August 22, 2002
    Inventors: Takuya Kobayashi, Satoshi Inami, Masashige Mizuyama, Atsunobu Kato, Hidehiko Shin, Hiromi Wada
  • Publication number: 20020099783
    Abstract: An information terminal device 10 is connected to a server 1 storing instruction data 200. For the received instruction data 200, a determining unit 104 determines the corresponding application. An analyzing unit 105 analyzes the instruction data 200. An operation control unit 106 extracts message data from the instruction data 200. An application executing unit 107 operates based on the instruction data and the above application. A display unit 19 displays a message represented by the message data on a screen based on the execution of the application. With an execution checking unit further provided, it is possible to determine whether the application is to be executed based on the message data.
    Type: Application
    Filed: January 17, 2002
    Publication date: July 25, 2002
    Inventors: Masashige Mizuyama, Takuya Kobayashi, Atsunobu Kato, Hidehiko Shin, Satoshi Inami
  • Publication number: 20020099718
    Abstract: A terminal-side communications control unit 41 makes a request to a server for retrieving an instruction file that describes an instruction for transmitting transmission data. The server transmits the instruction file in response to the request for retrieving the instruction file. On receiving the instruction file, the terminal-side communications control unit 41 causes an application executing unit 42 to execute an application, and also forwards the instruction file to a transmission data generating unit 44. On receiving the instruction file, the transmission data generating part 44 refers to the instruction file to generate, from generated data stored in a generated data storage unit 43, transmission data to be transmitted to the server.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 25, 2002
    Inventors: Satoshi Inami, Takako Hirose, Masashige Mizuyama, Atsunobu Kato, Munehito Matsuda, Hidehiko Shin, Hiromi Wada
  • Publication number: 20020099805
    Abstract: In a communications terminal 3, a CPU 32 retrieves start-up data 112 from a server 1 using a Web browser 311, which is stored in a storage device 31. The CPU 32 performs data authentication with respect to authentication type data 1123 included in the start-up data 112. Then, when the authentication is succeeded, the CPU 32 follows the authentication type data 1123 so as to determine which authentication mode is to be used for authenticating the application data. In this manner, the authentication mode for authenticating the application data can be easily changed.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 25, 2002
    Inventors: Satoshi Inami, Masashige Mizuyama, Atsunobu Kato