Patents by Inventor Masataka Aoshima

Masataka Aoshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220287308
    Abstract: A compound, or a salt thereof, is expressed by General Formula (1): wherein R represents a (C1-C6) alkoxy (C1-C6) alkyl group, which is useful as an agricultural and horticultural insecticide with reduced harmful effects to animals including humans in production of agricultural, horticultural and other crops.
    Type: Application
    Filed: August 6, 2020
    Publication date: September 15, 2022
    Inventors: Nobuyuki HAYASHI, Yoshinori GOSHO, Masataka AOSHIMA, Hiroko SATO
  • Patent number: 6915470
    Abstract: In a data log acquisition circuit 100, the number of executed test patterns counted by a number-of-patterns counter 1, or the address of the test pattern is compared with a predetermined reference value by an identity detection circuit 2. If the number of executed test patterns or the address of the test pattern and the predetermined reference value are data for the same test pattern, an identity signal is supplied to a log mode control circuit 3. The address of the test pattern is written into a log memory 6 at timing adjusted by a timing adjustment circuit 4 correspondingly to a write address of a data log generated by a counter 5 in accordance with an established operation mode. The write address and the address of the test pattern are held temporarily by a flip-flop 9. The number of generated FAIL signals is counted and outputted by a counter 10.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: July 5, 2005
    Assignee: Ando Electric Co., Ltd.
    Inventor: Masataka Aoshima
  • Publication number: 20020083040
    Abstract: In a data log acquisition circuit 100, the number of executed test patterns counted by a number-of-patterns counter 1, or the address of the test pattern is compared with a predetermined reference value by an identity detection circuit 2. If the number of executed test patterns or the address of the test pattern and the predetermined reference value are data for the same test pattern, an identity signal is supplied to a log mode control circuit 3. The address of the test pattern is written into a log memory 6 at timing adjusted by a timing adjustment circuit 4 correspondingly to a write address of a data log generated by a counter 5 in accordance with an established operation mode. The write address and the address of the test pattern are held temporarily by a flip-flop 9. The number of generated FAIL signals is counted and outputted by a counter 10.
    Type: Application
    Filed: October 25, 2001
    Publication date: June 27, 2002
    Inventor: Masataka Aoshima