Abstract: A pulse signal transfer control circuit is located between an input pulse detecting circuit for detecting the arrival of an externally applied input pulse and outputting a pulse signal with a predetermined pulse width, and an R-S flip-flop. The transfer control circuit prohibits the pulse signal from being transferred to the R-S flip-flop during a period in which the R-S flip-flop is set, a period of generation of a first internal clock signal, and a period of generation of a second internal clock signal, and allows the pulse signal to be transferred to the first R-S flip-flop during period in which the first and second clock signals are not generated and the period in which the first R-S flip-flop is reset.

Abstract: In a first conductivity type semiconductor substrate a plurality of second conductivity type regions are formed. First conductivity type resistivity regions are formed in the second conductivity type regions, respectively. The first conductivity type resistive regions are connected in series between power source terminals, through at least one divided potential taking-out electrode.

Abstract: In a semiconductor substrate of a first conductivity type fixed at a predetermined potential are formed a plurality of resistive regions of a second conductivity type. The resistive regions are connected in series between first and second potential supply terminals, through equally divided potential taking-out electrodes formed on the substrate. The resistive regions are so formed as to be progressively decreased in length in the order that the potential difference between the resistive region and the substrate increases to cause the resistive regions to have the substantially equal resistance values.

Abstract: An electronic apparatus comprises a timer circuit driven for a given time in response to a key input, complementary MOS transistor clocked dynamic logic circuits each with an output storage capacitance, clock signal supply souce for supplying complementary clock signals to the clocked dynamic logic circuits during the operative period of the timer circuit, and for supplying voltages with fixed levels to the clocked logic circuits during the inoperative period of the timer circuit. During the inoperative period, the output capacitance of the clocked logic circuit is fixed at a fixed potential level. This prevents the simultaneous turning-on of the complementary transistors in a succeeding logic circuit connected to the clocked logic circuits, resulting in little power consumption even when a power switch is not used.

Abstract: A voltage dividing circuit provides an intermediate level potential or intermediate level potentials between the maximum and minimum level potentials necessary for dynamic- or scanning-driving a liquid crystal display device. The voltage dividing circuit includes at least one insulated gate field effect transistor and a plurality of resistive elements each with relatively small resistance connected in series between power source terminals. The insulated gate field effect transistor is enabled during a fixed time interval at the initial stage of one display cycle to provide drive voltage to the liquid crystal display device with low output resistance. A first dividing circuit including low resistive elements enabled by an insulated gate field effect transistor or transistors may be connected in parallel with a second dividing circuit including relatively high resistive elements which provides the intermediate level potential or potentials with the same level as of the first dividing circuit.

Abstract: A complementary MOS logic circuit for obtaining second logic signals corresponding to a large number of logic combinations derived from a group of first logic signals, wherein a plurality of series circuits each formed of a plurality of series-connected first channel type IG-FET's and a plurality of series circuits each formed of a plurality of series-connected second channel type IG-FET's are jointly connected to the output terminal of said complementary MOS type logic circuit; the gates of the first and second channel type IG-FET's are supplied with first logic signals and those complementary thereto to specify a desired block circuit consisting of the component series circuits formed of the first and second channel type IG-FET's; and a second logic signal is conducted to the output terminal through the specified block circuit.

Abstract: A counter comprises a cascade connection of an inverter stage and n one-bit shift register stages, the latter being operative in response to clock signals to be counted and each having a data-readin or front half-bit shift register stage and a data-readout or rear half-bit shift register stage. The output of the final stage in the cascade connection is coupled to the input of the first stage in the cascade connection. The output of the final stage is also coupled to an additional input of consecutive 1st to X-th shift register stages or consecutive 2nd to (X-1)-th shift register stages of an X-th shift register stage to constitute a scale-of-2n-X or 2n-(X-1) counter.

Abstract: A method of manufacturing semiconductor devices is disclosed which includes the steps of forming an insulating film on one surface of a semiconductor substrate, removing the insulating film selectively to expose at least a portion of one surface of the semiconductor substrate, forming a low temperature oxide film containing a first diffusion source which has a higher etch rate than the insulating film onto at least a part of the exposed surface while leaving the rest of the surface exposed, and heating the substrate to diffuse the first diffusion source film from the oxide film into the substrate and to diffuse a second diffusion source through the exposed surface into the substrate thereby at least two diffused regions can be formed on the substrate without relative displacement.

Abstract: A level shifting circuit device comprises a first terminal connected to a high voltage power source, a P channel type IG-FET whose source and substrate electrodes are connected to said first terminal, means for applying a first pulse signal to the gate electrode of the P channel IG-FET, an N channel type IG-FET whose drain electrode is connected to the drain electrode of the P channel type IG-FET, an output terminal connected to a connecting point for connecting the drain electrodes of the P channel type and N channel type IG-FET's means for applying a specified voltage to the gate electrode of the N channel type IG-FET, an OR gate so connected as to supply an output to the source electrode of the N channel type IG-FET, means for supplying to the input terminals of the OR gate a second pulse signal synchronized with the first pulse signal and a low amplitude logic signal from the immediately preceding logic circuit to the level shifting circuit device, a capacitor connected between the substrate electrode of

Abstract: A logical circuit comprises a circuit having a plurality of insulated gate field effect transistors of different channel types and three terminals to which are connected corresponding voltage sources each having a different voltage level, and means for supplying first, second and third logical signals having the maximum and minimum voltage levels of the above-mentioned three different voltage levels to the circuit so that only one current path is always created between an output terminal of the circuit and any one of the three terminals. As a result, the logical circuit can generate an output having three logical levels.