Patents by Inventor Masataka Horai
Masataka Horai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7316745Abstract: A high-resistance silicon wafer is manufactured, in which a gettering ability and economical efficiency is excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is to be implemented on the side of a device manufacturer. In order to implement the above, a high-temperature heat treatment at 1100° C. or higher is performed on a carbon doped high-resistance and high-oxygen silicon wafer in which specific resistivity is 100 ?cm or more and a carbon concentration is 5×1015 to 5×1017 atoms/cm3 so that a remaining oxygen concentration becomes 6.5×1017 atoms/cm3 or more (Old-ASTM). As this high-temperature treatment, an OD treatment for forming a DZ layer on a wafer surface, a high-temperature annealing treatment for eliminating a COP on the surface layer, a high-temperature heat treatment for forming a BOX layer in a SIMOX wafer manufacturing process and the like can be used.Type: GrantFiled: June 30, 2003Date of Patent: January 8, 2008Assignee: Sumco CorporationInventors: Shinsuke Sadamitsu, Nobumitsu Takase, Hiroyuki Takao, Koji Sueoka, Masataka Horai
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Publication number: 20050250349Abstract: A high-resistance silicon wafer is manufactured, in which a gettering ability and economical efficiency is excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is to be implemented on the side of a device manufacturer. In order to implement the above, a high-temperature heat treatment at 1100° C. or higher is performed on a carbon doped high-resistance and high-oxygen silicon wafer in which specific resistivity is 100 ?cm or more and a carbon concentration is 5×1015 to 5×1017 atoms/cm3 so that a remaining oxygen concentration becomes 6.5×1017 atoms/cm3 or more (Old-ASTM). As this high-temperature treatment, an OD treatment for forming a DZ layer on a wafer surface, a high-temperature annealing treatment for eliminating a COP on the surface layer, a high-temperature heat treatment for forming a BOX layer in a SIMOX wafer manufacturing process and the like can be used.Type: ApplicationFiled: June 30, 2003Publication date: November 10, 2005Applicant: SUMITOMO MITSUBISHI SILICON CORPORATIONInventors: Shinsuke Sadamitsu, Nobumitsu Takase, Hiroyuki Takao, Koji Sueoka, Masataka Horai
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Patent number: 6878451Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016-5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer. The present invention provides an epitaxial wafer for a large-scale integrated device having no defects in a device-active region and having an excellent gettering effect without performance of an extrinsic or intrinsic gettering treatment, which is a factor for increasing the number of production steps and production costs.Type: GrantFiled: March 11, 2003Date of Patent: April 12, 2005Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Eiichi Asayama, Masataka Horai, Hiroki Murakami, Takayuki Kubo
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Patent number: 6835245Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.Type: GrantFiled: June 20, 2001Date of Patent: December 28, 2004Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Tadami Tanaka, Eiichi Asayama, Hideshi Nishikawa, Masataka Horai
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Publication number: 20040216659Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016-5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer.Type: ApplicationFiled: May 19, 2004Publication date: November 4, 2004Inventors: Eiichi Asayama, Masataka Horai, Hiroki Murakami, Takayuki Kubo
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Patent number: 6709957Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 atoms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.Type: GrantFiled: June 18, 2002Date of Patent: March 23, 2004Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Eiichi Asayama, Yasuo Koike, Tadami Tanaka, Toshiaki Ono, Masataka Horai, Hideshi Nishikawa
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Patent number: 6641888Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016−5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer. The present invention provides an epitaxial wafer for a large-scale integrated device having no defects in a device-active region and having an excellent gettering effect without performance of an extrinsic or intrinsic gettering treatment.Type: GrantFiled: January 25, 2002Date of Patent: November 4, 2003Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Eiichi Asayama, Masataka Horai, Shigeru Umeno, Shinsuke Sadamitsu, Yasuo Koike, Kouji Sueoka, Hisashi Katahama
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Publication number: 20030175532Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016-5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer.Type: ApplicationFiled: March 11, 2003Publication date: September 18, 2003Applicant: SUMITOMO METAL INDUSTRIES, LTD.Inventors: Eiichi Asayama, Masataka Horai, Hiroki Murakami, Takayuki Kubo
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Publication number: 20030104222Abstract: The invention relates to a silicon wafer and an epitaxial silicon wafer, which are doped with arsenic (As) as an n-type dopant and are excellent in gettering characteristics. A first silicon wafer has a resistivity of 10 &OHgr;cm to 0.001 &OHgr;cm as a result of addition of arsenic and has a nitrogen concentration of 1×1013 to 1×1015 atoms/cm3. A second silicon wafer has a resistivity of 0.1 &OHgr;cm to 0.005 &OHgr;cm and a nitrogen concentration of 1×1014 to 1×1015 atoms/cm3. A third silicon wafer has a resistivity of 0.005 &OHgr;cm to 0.001 &OHgr;cm and a nitrogen concentration of 1×1013 to 3×1014 atoms/cm3. An epitaxial silicon wafer derived from any of the first to third silicon wafers by forming an epitaxial layer in the surface layer portion is provided.Type: ApplicationFiled: September 18, 2002Publication date: June 5, 2003Inventors: Toshiaki Ono, Masataka Horai
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Publication number: 20030008447Abstract: The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1×1013 at ms/cm3 of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700° C. but lower than 900° C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11×1017 atoms/cm3. Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot.Type: ApplicationFiled: June 18, 2002Publication date: January 9, 2003Inventors: Eiichi Asayama, Yasuo Koike, Tadami Tanaka, Toshiaki Ono, Masataka Horai, Hideshi Nishikawa
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Publication number: 20020142170Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016−5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer.Type: ApplicationFiled: January 25, 2002Publication date: October 3, 2002Applicant: SUMITOMO METAL INDUSTRIES, LTD.Inventors: Eiichi Asayama, Masataka Horai, Hiroki Murakami, Takayuki Kubo, Shigeru Umeno, Shinsuke Sadamitsu, Yasuo Koike, Kouji Sueoka, Hisashi Katahama
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Publication number: 20020142171Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016-5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer.Type: ApplicationFiled: January 25, 2002Publication date: October 3, 2002Applicant: SUMITOMO METAL INDUSTRIES, LTD.Inventors: Eiichi Asayama, Masataka Horai, Hiroki Murakami, Takayuki Kubo, Shigeru Umeno, Shinsuke Sadamitsu, Yasuo Koike, Kouji Sueoka, Hisashi Katahama
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Publication number: 20020017234Abstract: Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3° C./min in the temperature range of 1200-1050° C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1×1012 atoms/cm3 to 1×1014 atoms/cm3 as produced by employing a cooling rate of not less than 2.7° C./min in the temperature range of 1150-1020° C. and then a cooling rate of not more than 1.2° C./min in the temperature range of 1000-850° C. in the step of pulling up thereof.Type: ApplicationFiled: June 20, 2001Publication date: February 14, 2002Applicant: Sumitomo Metal Industries, Ltd., Osaka-shi, JapanInventors: Toshiaki Ono, Tadami Tanaka, Eiichi Asayama, Hideshi Nishikawa, Masataka Horai
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Patent number: 6113687Abstract: A silicon single crystal wafer having good device characteristics can be manufactured according to the Czochralski method without formation of any dislocation cluster within a crystal surface. Where a silicon single crystal having an oxygen concentration of less than 8.5.times.10.sup.17 atoms/cm.sup.3 (ASTM F1188-88) is manufactured, a radius of a latent zone of oxidation induced stacking defects ring-likely-distributed in the crystal surface is made within a range of 70% to 0% of a crystal radius, and a value of V/G (mm.sup.2 /.degree. C..multidot.minute) is controlled at a predetermined critical value or over at radial positions except an outermost periphery of the crystal when a pulling rate is taken as V (mm/minute), and a crystalline temperature gradient along the pulling axis is taken as G (.degree. C./mm). On the other hand, when a silicon single crystal having an oxygen concentration of not less than 8.5.times.10.sup.17 atoms/cm.sup.Type: GrantFiled: November 17, 1998Date of Patent: September 5, 2000Assignee: Sumitomo Metal Industries, Ltd.Inventors: Masataka Horai, Kazuyuki Egashira, Tadami Tanaka
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Patent number: 5508207Abstract: The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.Type: GrantFiled: April 26, 1994Date of Patent: April 16, 1996Assignee: Sumitomo Sitix CorporationInventors: Masataka Horai, Naoshi Adachi, Hideshi Nishikawa, Masakazu Sano