Patents by Inventor Masataka Kimoto

Masataka Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153268
    Abstract: The participant terminal 80 includes imaging means 81 for shooting video of the participant who uses the participant terminal 80, frequency measurement means 82 for measuring the number of nods of the participant from the shot video, and action information transmission means 83 for transmitting action information that information of the participant is associated with the number of nods to the server 70. The server 70 includes transmission means 71 for transmitting the action information to the speaker terminal 90. The speaker terminal 90 includes participant output means 91 for outputting the information of the participant in order according to the number of nods included in the action information.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 9, 2024
    Applicant: NEC Corporation
    Inventors: Toshihiko FUJISAKI, Atsushi KUBO, Masataka SUGIMOTO, Makoto KIMOTO
  • Patent number: 5991889
    Abstract: In a microcomputer including a program memory (1) and a CPU (2) operable in one of high-speed and low-speed modes in which the CPU carries out high-speed and low-speed operations when supplied with high-speed and low-speed clock signals (CKH and CKL), respectively, the program memory includes high-speed and low-speed operation memories (11 and 12) for memorizing high-speed and low-speed mode programs which are read by first and second predetermined address ranges of a program address of a program counter (21) of the CPU and which make the CPU carry out the high-speed and the low-speed operations, respectively. A memory controller (3) produces, when detects the second predetermined address range of the program address, a high-speed operation stop signal for stopping operation of the high-speed operation memory. A clock supplying circuit (4) supplies the CPU with one of the high-speed and the low-speed clock signals that corresponds to one of the high-speed and the low-speed modes.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: November 23, 1999
    Assignee: NEC Corporation
    Inventors: Hiroshi Hikichi, Masataka Kimoto