Abstract: In a static memory, a memory cell is constituted by only the same-channel MOSFETs. With the MOSFETs of the same channel, no well isolation region is required, and a cell size can be decreased. Moreover, the high potential side power source of a flip-flop can be used as a read word line. Thus the read word line can be driven by an ECL logic circuit.

Abstract: The coating method contains a spraying step in which a paint is sprayed at least on a coating substrate extending in an upward and downward direction to a film thickness thicker than causing sags of the sprayed paint. The coating substrate on which the paint is sprayed is rotated about the horizontal axis while the sprayed paint is dried until it does not sag any more. The coating apparatus includes a carriage conveying the coating substrate arranged to run along the conveying direction, and the carriage is provided with a supporting base for supporting the coating substrate rotatively about the horizontal axis. One embodiment for rotating the substrate supported by the supporting base is a spring that is disposed on the carriage to rotate the substrate by means of a restoring force produced by the spring. On the passage for conveying the carriage is disposed a force storing mechanism for storing the restoring force in the spring that released the restoring force.

Abstract: An address transition detecting circuit detects on address transition signal generated during the writing of input data into a static random access memory (SRAM) and generates an address detection signal as a monostable pulse of a predetermined length. A bit line precharge and equalize signals generating circuit generates, in synchronization with the address transition detection signal and an input signal on a write data line, a bit line precharge signal and bit line equalize signal which are supplied to their columns in memory. At a time of reading, the bit line precharge and equalize signals generating circuit supplies a high level potential to paired data lines to prevent a data entry from being made into the paired write data lines by a resetting operation.

Abstract: A voltage generating circuit includes a first current source which generates a first current and a first voltage generating circuit which generates a first voltage having a first temperature dependency. A second voltage generating circuit generates a second voltage having a second temperature dependency different than the first temperature dependency. A voltage adder circuit coupled to the first and second voltage generating circuits adds the first and second voltages to generate a third voltage having no temperature dependency. A voltage replicating circuit coupled to the voltage adder circuit coupled to the voltage adder circuit replicates the third voltage as a fourth voltage having a level corresponding to the third voltage. A second current source generates a constant second current through a resistive element biased by the fourth voltage and a current replicating circuit coupled to the first and second current sources replicates the second current as the first current.

Abstract: A semiconductor logic circuit includes a bipolar totem pole buffer. The buffer is made up of a first npn bipolar transistor whose collector-emitter path is connected between a first power source node and an output node, and a second npn bipolar transistor whose collector-emitter path is connected between the output node and a second power source node. A third npn bipolar transistor is connected at the collector and the base to the base of the second npn bipolar transistor, and at the emitter to the second power source node. An output transistor drive circuit includes a MOS transistor. The drain-source path of the MOS transistor is connected between a third power source node, which is placed at one of potentials equal to and lower than the potential of the first power source node, and the base of the second npn bipolar transistor. The gate of the MOS transistor is connected to a signal input node.

Abstract: A CMOS static memory includes a memory cell array having a plurality of memory cells two-dimensionally arranged in word and bit line directions, and peripheral circuits including n-type MOSFETs for performing a write/read operation for the memory cell. The memory cell includes a flip-flop circuit constituted by a pair of pull-down n-type MOSFETs and a pair of pull-up resistor elements, and a pair of transmission gate n-type MOSFETs. Each of a pair of pull-down n-type MOSFETs and the pair of transmission gate n-type MOSFETs have a gate oxide film having a thickness and gate length which are smaller than those of a gate oxide film of each n-type MOSFET in the peripheral circuits.

Abstract: A logic level converting circuit for converting an ECL level signal to a CMOS level signal comprises complementary signal generating means and level shifting means. The complementary signal generating means generates complementary signals in response to the ECL level input signal and a first reference voltage. The level shifting means operates as a flip-flop circuit, and includes a first and a second PMOS transistors which are either conductive or not conductive in response to the relationship between the complementary signals and a second reference voltage applied to the gate electrodes of the PMOS transistors.

Abstract: A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.

Abstract: A static random access memory comprising a semiconductor substrate, a well region formed in the substrate and containing at least one memory cell, and a power-supply terminal connected to the well region, for applying a given bias voltage to the well region.

Abstract: A static random access memory device is comprised of a write mode detector for detecting a signal state transition of a write enable signal changing to an active state, an input data transition detector for detecting a transition of the input data supplied from exterior, during a contamination of the active state of the write enable signal, a power down timer for generating a pulse signal with a predetermined pulse width in response to either of the detecting signals outputted from the write mode detector and input data transition detector, a gate circuit for permitting the output data from a row decoder to be transferred to memory cells during a period that the power down timer generates a pulse signal, and for inhibiting that data transfer during a period that the power down timer rests, and a write circuit control circuit allowing a write circuit to supply write data to the bit line pair during a period that the power down timer generates a pulse signal, and prohibiting that write data transfer during a pe

Abstract: A row address signal is supplied to a row address input buffer, and a column address signal is supplied to a column address input buffer. The row address signal supplied to the row address input buffer is then supplied to a row main decoder, through a row address predecoder, the column address signal supplied to the column address input buffer being supplied to a column address predecoder. An output from the column address predecoder is supplied to a filter or delay circuit, and an output signal from the filter or delay circuit is supplied to a column main decoder. One memory cell in a memory cell array is selected in response to decode outputs from the row main decoder and the column main decoder, and readout data of the selected memory cell is amplified by a sense amplifier. An output from the sense amplifier is output through a data output circuit and a data output buffer.

Abstract: A static semiconductor memory comprises a word line, a memory cell array divided into a plurality of blocks in an extending direction of the word line, each block including a plurality of sections each of which includes a plurality of static memory cells, a controller, a section data line provided for each section, first sense amplifiers, a block data line provided for each block, second sense amplifiers, a main data line and a latch circuit for latching data on the main data line. The controller selects an arbitrary section in the memory cell array at the time of data readout and controls the reading of data from memory cells included in the selected section. The section data line is supplied with data read out from the memory cells. The first sense amplifiers, coupled at their input terminals to the section data line, are activated only when their associated section is selected. The individual first sense amplifiers in the same block have their output terminals commonly coupled to the block data line.

Abstract: When an address transition detector detects a transition of an address signal, it produces an address transition detect signal. The signal drives a bit line initializing circuit which in turn initializes paired bit lines, and initializes the paired output lines of a sense amplifier. At the same time, a clock signal generator generates a clock signal for a predetermined period of time in accordance with the address transition detect signal. The clock signal is supplied to the sense amplifier and a data output circuit. The sense amplifier is active during a period that the clock signal from the clock signal generator is in an effective level. The output terminal of the data output circuit is placed in a high impedance state during the period that the clock signal is in an effective level. During the other periods than the effective level period, the data output circuit produces a signal corresponding to the data as is read out of a memory cell and outputted by the sense amplifier.

Abstract: A memory cell array includes a plurality of static memory cells arranged in a matrix form and selectively controlled by means of word lines to output complementary memory data to paired bit lines. An address transition detecting circuit generates an address transition signal in the form of a monostable pulse having a constant length when detecting the transition of an address signal. A bit line initializing circuit initializes the potentials of the paired bit lines in synchronism with the address transition signal. A pulse width extension circuit sets the pulse width of the address transition signal generated from the address transition detecting circuit to be longer in the write mode than in the readout mode.

Abstract: A static random access memory comprising a memory cell array, a plurality of peripheral circuits, first and second power-supply voltage lines, a bonding pad, and a level-shifting circuit. The array has static memory cells each having resistors functioning as load elements. The peripheral circuits control the writing of data into, and the reading of data from, the static memory cells. The first power-supply voltage line applies a first power-supply voltage to the peripheral circuits. The bonding pad is connected to the first power-supply voltage line. The second power-supply voltage line applies a second power-supply voltage to the static memory cells. The level-shifting means is connected between the first and second power-supply voltage lines, for shifting the level of the first power-supply voltage and applying the level-shifted voltage to the static memory cells via said second power-supply voltage line.

Abstract: In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it.

Abstract: The coating method contains a spraying step in which a paint is sprayed at least on a coating substrate extending in an upward and downward direction to a film thickness thicker than causing sags of the sprayed paint. The coating substrate on which the paint is sprayed is rotated about the horizontal axis while the sprayed paint is dried until it does not sag any more.The coating apparatus includes a carriage conveying the coating substrate arranged to run along the conveying direction, and the carriage is provided with a supporting base for supporting the coating substrate rotatively about the horizontal axis. One embodiment for rotating the substrate supported by the supporting base is a spring that is disposed on the carriage to rotate the substrate by means of a restoring force produced by the spring. On the passage for conveying the carriage is disposed a force storing mechanism for storing the restoring force in the spring that released the restoring force.

Abstract: In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function.

Abstract: The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.

Abstract: A Bi-CMOS logic circuit having a totem pole-type output buffer, a CMOS logic circuit, and a latch circuit. The output buffer comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. The CMOS logic circuit controls the base current of the pull-up NPN bipolar transistor. The latch circuit controls the base current of the pull-down NPN bipolar transistor. The latch circuit includes at least two N-type MOSFETs. The first MOSFET has a gate coupled to the input terminal of the CMOS logic circuit, a drain connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor. The second MOSFET has a drain coupled to the input terminal of the CMOS logic circuit, a gate connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.