Patents by Inventor Masataka Minami

Masataka Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210292699
    Abstract: The device has a film-shaped main body part 1, and predetermined region in the film surface of the main body part has a mesh structure in which a large number of through-holes 20 are arranged. The through-hole has an opening shape having a size allowing smaller cell aggregates to pass through, and the rest of the through-hole is the beam part 30. The beam part is a part that cuts a cell aggregate to be divided, and is integrally connected to form a network. The cell aggregate can be divided by passing the cell aggregate to be divided through the mesh structure of the device together with the liquid.
    Type: Application
    Filed: August 6, 2019
    Publication date: September 23, 2021
    Applicant: NISSAN CHEMICAL CORPORATION
    Inventors: Keiichiro OTSUKA, Masataka MINAMI, Hisato HAYASHI
  • Patent number: 10659026
    Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masataka Minami
  • Publication number: 20200040304
    Abstract: The present invention provides a cell carrier containing a nanofiber composed of water-insoluble polysaccharides, preferably chitin or chitosan nanofiber; a carrier capable of being a common carrier in various operations such as i) suspension culture, ii) differentiation induction, iii) transportation and preservation under non-freezing conditions, iv) transplantation, v) recovery of bioactive substance from culture supernatant and the like of adherent cells; and continuous performance of plural operations selected from i) suspension culture, ii) differentiation induction, iii) transportation and preservation under non-freezing conditions, iv) transplantation, and v) recovery of bioactive substance from culture supernatant of adherent cells by using the carrier.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 6, 2020
    Applicant: NISSAN CHEMICAL CORPORATION
    Inventors: Tatsuro KANAKI, Katsuhiko KIDA, Hisato HAYASHI, Masataka MINAMI
  • Patent number: 10385052
    Abstract: Novel tricyclic compounds which have JAK inhibitory activities are useful for prevention, treatment or improvement of autoimmune diseases, inflammatory diseases and allergic diseases are provided. Novel tricyclic compound represented by the formula (I), the formula (II) or the formula (III) (wherein: each of A1, A2 and A3 is a cyclohexane-1,4-diyl group or the like; each of L1, L2 and L3 is a methylene group or the like; each of X1 and X3 is O or NH; each of R1 and R3 is a cyano C1-6 haloalkyl group or the like; and R2 is an aromatic heterocyclic group), a tautomer or pharmaceutically acceptable salt of the compound or a solvate thereof.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 20, 2019
    Assignee: Nissan Chemical Corporation
    Inventors: Tsuneo Watanabe, Keiji Takahashi, Keishi Hayashi, Takanori Nakamura, Masataka Minami, Kazunori Kurihara, Akio Yamamoto, Takuya Nishimura, Miyuki Uni, Toshihiko Kamiyama, Shunsuke Iwamoto
  • Patent number: 10371582
    Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: August 6, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Obayashi, Hiroki Shimano, Masataka Minami, Hiroji Ozaki
  • Publication number: 20190123729
    Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
    Type: Application
    Filed: August 10, 2018
    Publication date: April 25, 2019
    Inventor: Masataka Minami
  • Publication number: 20180261607
    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Application
    Filed: May 9, 2018
    Publication date: September 13, 2018
    Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
  • Patent number: 10041841
    Abstract: A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Arisaka, Masataka Minami, Takahiro Miki
  • Patent number: 9985038
    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: May 29, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
  • Publication number: 20180128689
    Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 10, 2018
    Inventors: Shigeki OBAYASHI, Hiroki SHIMANO, Masataka MINAMI, Hiroji OZAKI
  • Publication number: 20180099966
    Abstract: Novel tricyclic compounds which have JAK inhibitory activities are useful for prevention, treatment or improvement of autoimmune diseases, inflammatory diseases and allergic diseases are provided. Novel tricyclic compound represented by the formula (I), the formula (II) or the formula (III) (wherein: each of A1, A2 and A3 is a cyclohexane-1,4-diyl group or the like; each of L1, L2 and L3 is a methylene group or the like; each of X1 and X3 is 0 or NH; each of R1 and R3 is a cyano C1-6 haloalkyl group or the like; and R2 is an aromatic heterocyclic group), a tautomer or pharmaceutically acceptable salt of the compound or a solvate thereof.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Tsuneo Watanabe, Keiji Takahashi, Keishi Hayashi, Takanori Nakamura, Masataka Minami, Kazunori Kurihara, Akio Yamamoto, Takuya Nishimura, Miyuki Uni, Toshihiko Kamiyama, Shunsuke Iwamoto
  • Publication number: 20180073935
    Abstract: A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventors: Naoya ARISAKA, Masataka MINAMI, Takahiro MIKI
  • Patent number: 9890165
    Abstract: Novel tricyclic compounds which have JAK inhibitory activities are useful for prevention, treatment or improvement of autoimmune diseases, inflammatory diseases and allergic diseases are provided. Novel tricyclic compound represented by the formula (I), the formula (II) or the formula (III) (wherein: each of A1, A2 and A3 is a cyclohexane-1,4-diyl group or the like; each of L1, L2 and L3 is a methylene group or the like; each of X1 and X3 is O or NH; each of R1 and R3 is a cyano C1-6 haloalkyl group or the like; and R2 is an aromatic heterocyclic group), a tautomer or pharmaceutically acceptable salt of the compound or a solvate thereof.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: February 13, 2018
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Tsuneo Watanabe, Keiji Takahashi, Keishi Hayashi, Takanori Nakamura, Masataka Minami, Kazunori Kurihara, Akio Yamamoto, Takuya Nishimura, Miyuki Uni, Toshihiko Kamiyama, Shunsuke Iwamoto
  • Patent number: 9891116
    Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: February 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeki Obayashi, Hiroki Shimano, Masataka Minami, Hiroji Ozaki
  • Patent number: 9882915
    Abstract: Device control method including: operation receiving step of receiving a device control operation for controlling a device; determining step of determining whether an operation terminal is in a first state or a second state; limiting step of, when determined in the determining step that the operation terminal is in the second state, limiting a range of controls of the device made available to the operation terminal when in the second state so as to correspond to part of a range of controls of the device made available to the operation terminal when in the first state; and device controlling step of controlling the device based on the device control operation. When determined in the determining step that the operation terminal is in the second state, the device is controlled within the range of controls of the device made available to the operation terminal when in the second state.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: January 30, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshihisa Nakano, Masayuki Kozuka, Masataka Minami, Motoji Ohmori, Takeshi Matsuo, Tsuyoshi Sakata, Fumiaki Suzuki
  • Patent number: 9835499
    Abstract: The present invention provides a semiconductor device having a sensor capable of improving precision while suppressing increase in occupation area. A semiconductor device has: a first counter; and a second counter (time measuring circuit) measuring time until a count value, which is obtained by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the first counter. The first counter obtains a piece of digital information corresponding to the first voltage on the basis of a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, on the basis of the time measured by the time measuring circuit.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Arisaka, Masataka Minami, Takahiro Miki
  • Patent number: 9774608
    Abstract: A device control method used in a device control system in which an operation terminal is used to remotely operate a device with a server device mediating between the operation terminal and the device, the device control method including: acquiring, upon reception of an operation instruction for operation of the device from the operation terminal, environment information pertaining to at least one of the device and the operation terminal; performing a determination of whether or not to cause execution of processing corresponding to the operation instruction based on whether or not the environment information satisfies a predetermined condition; and causing the device to execute an execution command for execution of the processing when a result of the determination is affirmative, and not causing the device to execute the execution command when the result of the determination is negative.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: September 26, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshihisa Nakano, Masayuki Kozuka, Masataka Minami, Motoji Ohmori, Takeshi Matsuo, Tsuyoshi Sakata, Fumiaki Suzuki
  • Patent number: 9720391
    Abstract: A user-friendly cooperative process execution method for causing household electric devices that are registered to a server to execute cooperative processes. The server stores correspondence information associating a particular operation to be executed by a particular household electric device with one or more groups each composed of one or more household electric devices, and indicating, for each of the household electric devices in each of the groups, a control signal to be transmitted to the household electric device. The method includes: detecting whether or not the particular operation is executed; selecting one of the groups that is composed of one or more household electric devices that are registered to the server by referring to the correspondence information when the execution of the particular operation is detected; and transmitting the control signal to each of the household electric devices in the selected group.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: August 1, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Toshihisa Nakano, Masayuki Kozuka, Masataka Minami, Motoji Ohmori, Takeshi Matsuo, Tsuyoshi Sakata, Fumiaki Suzuki, Masao Nonaka, Ryota Miyazaki, Kazuo Kajimoto, Yoshiyuki Miyabe
  • Publication number: 20170179136
    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 22, 2017
    Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
  • Patent number: 9646678
    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: May 9, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi