Patents by Inventor Masataka Minami
Masataka Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094064Abstract: Before a temperature characteristic of a band gap reference circuit is tested, temperature dependencies of a reference voltage and an absolute temperature proportional voltage for a plurality of samples are measured. When the temperature characteristic is tested, based on a difference ?Vref between the reference voltage of the band gap reference circuit at a predetermined temperature and a median value of the reference voltages of the plurality of samples, a difference ?Vptat between the absolute temperature proportional voltage of the band gap reference circuit at a predetermined temperature and a median value of the absolute temperature proportional voltages of the plurality of samples is calculated.Type: ApplicationFiled: July 17, 2023Publication date: March 21, 2024Inventors: Tadashi KAMEYAMA, Fumiki KAWAKAMI, Tetsuhiro KOYAMA, Masataka MINAMI
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Patent number: 11762034Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.Type: GrantFiled: December 22, 2021Date of Patent: September 19, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadashi Kameyama, Masanori Ikeda, Masataka Minami, Kenichi Shimada, Yukitoshi Tsuboi
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Publication number: 20230159921Abstract: Provided is a translation enhancer that can shorten the 5?UTR. The object is achieved by a translation enhancer used in a cell-free protein synthesis system, the translation enhancer is a combination of a first sequence corresponding to nucleic acids as a 5? untranslated region connected adjacent to a 5? terminal of a code region that codes the amino acid sequence of the target protein, and a second sequence corresponding to nucleic acids as a 3? untranslated region connected adjacent to a 3? terminal of a code region that codes the amino acid sequence of the target protein, and the first sequence and the second sequence have complementary sequences that form conjugation.Type: ApplicationFiled: December 16, 2021Publication date: May 25, 2023Inventors: Satori MINAMI, Tomotaka ITAYA, Hiroaki TADA, Masataka MINAMI
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Publication number: 20220333121Abstract: The object is to provide a translation enhancer that improves synthesis efficiency of a target protein. The object is achieved by a translation enhancer in a cell-free protein synthesis system, and the translation enhancer consists of a nucleic acid as a 3? untranslated region linked adjacent to a 3? terminal of a code region that encodes an amino acid sequence of a target protein, the 3? untranslated region comprises a first region consisting of a sequence of 10 to 40 nucleic acids adjacent to the 3? terminal of the code region and a second region consisting of a poly-A sequence having continuous 2 to 40 “A”s linked to the first region, and the first region has a hairpin structure.Type: ApplicationFiled: September 24, 2020Publication date: October 20, 2022Inventors: Hiroaki TADA, Masataka MINAMI
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Publication number: 20220113357Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Tadashi KAMEYAMA, Masanori IKEDA, Masataka MINAMI, Kenichi SHIMADA, Yukitoshi TSUBOI
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Patent number: 11243264Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.Type: GrantFiled: April 22, 2020Date of Patent: February 8, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadashi Kameyama, Masanori Ikeda, Masataka Minami, Kenichi Shimada, Yukitoshi Tsuboi
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Publication number: 20210340491Abstract: The present invention provide a medium composition for suspension culture of an adherent cell, containing (1) a chitin nanofiber; and (2) a chitosan nanofiber or a polysaccharide.Type: ApplicationFiled: August 30, 2019Publication date: November 4, 2021Applicant: NISSAN CHEMICAL CORPORATIONInventors: Tatsuro KANAKI, Katsuhiko KIDA, Masataka MINAMI, Daisuke HATANAKA
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Publication number: 20210333333Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventors: Tadashi KAMEYAMA, Masanori IKEDA, Masataka MINAMI, Kenichi SHIMADA, Yukitoshi TSUBOI
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Publication number: 20210292699Abstract: The device has a film-shaped main body part 1, and predetermined region in the film surface of the main body part has a mesh structure in which a large number of through-holes 20 are arranged. The through-hole has an opening shape having a size allowing smaller cell aggregates to pass through, and the rest of the through-hole is the beam part 30. The beam part is a part that cuts a cell aggregate to be divided, and is integrally connected to form a network. The cell aggregate can be divided by passing the cell aggregate to be divided through the mesh structure of the device together with the liquid.Type: ApplicationFiled: August 6, 2019Publication date: September 23, 2021Applicant: NISSAN CHEMICAL CORPORATIONInventors: Keiichiro OTSUKA, Masataka MINAMI, Hisato HAYASHI
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Patent number: 10659026Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.Type: GrantFiled: August 10, 2018Date of Patent: May 19, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Masataka Minami
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Publication number: 20200040304Abstract: The present invention provides a cell carrier containing a nanofiber composed of water-insoluble polysaccharides, preferably chitin or chitosan nanofiber; a carrier capable of being a common carrier in various operations such as i) suspension culture, ii) differentiation induction, iii) transportation and preservation under non-freezing conditions, iv) transplantation, v) recovery of bioactive substance from culture supernatant and the like of adherent cells; and continuous performance of plural operations selected from i) suspension culture, ii) differentiation induction, iii) transportation and preservation under non-freezing conditions, iv) transplantation, and v) recovery of bioactive substance from culture supernatant of adherent cells by using the carrier.Type: ApplicationFiled: March 30, 2018Publication date: February 6, 2020Applicant: NISSAN CHEMICAL CORPORATIONInventors: Tatsuro KANAKI, Katsuhiko KIDA, Hisato HAYASHI, Masataka MINAMI
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Patent number: 10385052Abstract: Novel tricyclic compounds which have JAK inhibitory activities are useful for prevention, treatment or improvement of autoimmune diseases, inflammatory diseases and allergic diseases are provided. Novel tricyclic compound represented by the formula (I), the formula (II) or the formula (III) (wherein: each of A1, A2 and A3 is a cyclohexane-1,4-diyl group or the like; each of L1, L2 and L3 is a methylene group or the like; each of X1 and X3 is O or NH; each of R1 and R3 is a cyano C1-6 haloalkyl group or the like; and R2 is an aromatic heterocyclic group), a tautomer or pharmaceutically acceptable salt of the compound or a solvate thereof.Type: GrantFiled: December 13, 2017Date of Patent: August 20, 2019Assignee: Nissan Chemical CorporationInventors: Tsuneo Watanabe, Keiji Takahashi, Keishi Hayashi, Takanori Nakamura, Masataka Minami, Kazunori Kurihara, Akio Yamamoto, Takuya Nishimura, Miyuki Uni, Toshihiko Kamiyama, Shunsuke Iwamoto
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Patent number: 10371582Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.Type: GrantFiled: January 4, 2018Date of Patent: August 6, 2019Assignee: Renesas Electronics CorporationInventors: Shigeki Obayashi, Hiroki Shimano, Masataka Minami, Hiroji Ozaki
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Publication number: 20190123729Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.Type: ApplicationFiled: August 10, 2018Publication date: April 25, 2019Inventor: Masataka Minami
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Publication number: 20180261607Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.Type: ApplicationFiled: May 9, 2018Publication date: September 13, 2018Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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Patent number: 10041841Abstract: A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.Type: GrantFiled: November 20, 2017Date of Patent: August 7, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Arisaka, Masataka Minami, Takahiro Miki
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Patent number: 9985038Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.Type: GrantFiled: March 2, 2017Date of Patent: May 29, 2018Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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Publication number: 20180128689Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.Type: ApplicationFiled: January 4, 2018Publication date: May 10, 2018Inventors: Shigeki OBAYASHI, Hiroki SHIMANO, Masataka MINAMI, Hiroji OZAKI
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Publication number: 20180099966Abstract: Novel tricyclic compounds which have JAK inhibitory activities are useful for prevention, treatment or improvement of autoimmune diseases, inflammatory diseases and allergic diseases are provided. Novel tricyclic compound represented by the formula (I), the formula (II) or the formula (III) (wherein: each of A1, A2 and A3 is a cyclohexane-1,4-diyl group or the like; each of L1, L2 and L3 is a methylene group or the like; each of X1 and X3 is 0 or NH; each of R1 and R3 is a cyano C1-6 haloalkyl group or the like; and R2 is an aromatic heterocyclic group), a tautomer or pharmaceutically acceptable salt of the compound or a solvate thereof.Type: ApplicationFiled: December 13, 2017Publication date: April 12, 2018Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.Inventors: Tsuneo Watanabe, Keiji Takahashi, Keishi Hayashi, Takanori Nakamura, Masataka Minami, Kazunori Kurihara, Akio Yamamoto, Takuya Nishimura, Miyuki Uni, Toshihiko Kamiyama, Shunsuke Iwamoto
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Publication number: 20180073935Abstract: A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Inventors: Naoya ARISAKA, Masataka MINAMI, Takahiro MIKI