Patents by Inventor Masataka Muroga

Masataka Muroga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wiring substrate and semiconductor device each having first and second via wirings
    Patent number: 11823993
    Abstract: A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: November 21, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD
    Inventor: Masataka Muroga
  • WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
    Publication number: 20220130746
    Abstract: A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring.
    Type: Application
    Filed: October 22, 2021
    Publication date: April 28, 2022
    Inventor: Masataka Muroga