Abstract: An n-type diffused layer is formed in a p-type semiconductor substrate. A control gate electrode of a memory cell MC is connected with a metal interconnect of a first layer and the metal interconnect is connected with the diffused layer. Moreover, a metal interconnect of the first layer is connected with a metal interconnect of a second layer. An interconnect of the second layer is connected with the output node of a row decoder.

Abstract: A high-speed and highly-integrated semiconductor device and a producing method thereof, which can reduce resistance between a gate electrode and a wiring layer on the gate electrode and can make an element minute, are provided. The gate electrodes on a semiconductor substrate, diffusion layers formed in a surface region of the semiconductor substrate, buried electrodes formed on the semiconductor substrate so as to be connected to the diffusion layers respectively, an interlayer insulating film buried in spaces between the gate electrodes and in spaces between the gate electrodes and the buried electrodes, and wiring layers formed so as to be connected to the gate electrodes or to the buried electrodes are provided. A height of surfaces of the gate electrodes, a height of surfaces of the buried electrodes and a height of a surface of the interlayer insulating film are equal, and the surfaces of the gate electrodes, the buried electrodes and the interlayer insulating film form a plane.

Abstract: A semiconductor memory device includes different types of memory matrices adjacently arranged such that bit lines are aligned in the same cell matrix region, a column decoder for selecting the bit lines of the memory matrix, and a row decoder for selecting the row lines of the memory matrix. Therefore, a semiconductor memory device having many types of memory matrices can be highly integrated in the same cell matrix region in the same layout.

Abstract: According to this invention, a semiconductor non-volatile memory device includes a semiconductor substrate, insulating films formed on the semiconductor substrate and having at least two types of gate insulating films having different thicknesses and a first conductive film formed on the insulating films and electrically floating from the semiconductor substrate through the insulating films. These at least two types of gate insulating films include a first insulating film formed on said semiconductor substrate and a first diffusion layer of a conductivity type and a second insulating film formed on said semiconductor substrate and a second diffusion layer, of the opposite conductivity type, which is isolated from the first diffusion layer. The first conductive film is formed on the first and second insulating films.

Abstract: A non-volatile semiconductor memory device includes a voltage supply circuit for supplying a positive voltage to the source line or bit line (to which a low biasing voltage is conventionally applied) with respect to each of non-volatile memory cells in a memory cell array in a data read mode. Since this voltage supply circuit applies the positive voltage to the memory cells in the data read mode, an effect equivalent to back gate biasing of the memory cells can be achieved. Accordingly, a memory cell in an overerase state has, a positive threshold voltage in the data read mode.

Abstract: According to this invention, a semiconductor non-volatile memory device includes a semiconductor substrate, insulating films formed on the semiconductor substrate and having at least two types of gate insulating films having different thicknesses and a first conductive film formed on the insulating films and electrically floating from the semiconductor substrate through the insulating films. These at least two types of gate insulating films include a first insulating film formed on said semiconductor substrate and a first diffusion layer of a conductivity type and a second insulating film formed on said semiconductor substrate and a second diffusion layer, of the opposite conductivity type, which is isolated from the first diffusion layer. The first conductive film is formed on the first and second insulating films.

Abstract: In a method of manufacturing a semiconductor device, an Al wiring layer is formed on an interlevel insulator using a positive resist. The interlevel insulator has a recess portion formed on its surface corresponding to a position between two electrodes under the interlevel insulator. The Al wiring layer extends along the recess portion in the longitudinal direction and is formed to bridge the recess portion in a direction perpendicular to the logitudinal direction. The method includes the steps of arranging an Al layer on a region of the interlevel insulator including the recess portion, arranging the resist of the Al layer, exposing the resist to a light beam using a mask member having a light-shielding portion corresponding to the wiring layer, patterning the photoresist, and etching the Al layer using the patterned resist as a mask to form the wiring layer.

Abstract: A nonvolatile semiconductor memory device is disclosed, which includes a semiconductor substrate, a field oxidation film selectively formed on the semiconductor substrate, a first gate insulating film formed on an exposed surface of the semiconductor substrate and on the field oxidation film, a plurality of memory cells, floating gate electrodes and control gate electrodes of the plurality of memory cells, the floating gate and the control gate of each of the memory cells being isolated from those of other adjacent memory cells so as to be formed into an island, an insulating interlayer formed on the field oxidation film and on the control gate electrode, a contact hole extending through the first insulating interlayer so as to expose a portion of the control gate electrode, and a plurality of wires, formed on the insulating interlayer, for connecting the control gate electrodes of memory cells of the plurality of memory cells, which are adjacent to each other in a word line direction, through the first conta

Abstract: For improving endurance and retention characteristics of a nonvolatile semiconductor memory device that comprises a semiconductor substrate having source and drain regions therein, a floating gate provided above the semiconductor substrate through a first gate insulating film, a control gate provided above the flosting gate through a second gate insulating film, and a tunnel region provided in the first gate insulating film, an aperture is provided in the first gate insulating film so as to reach the semiconductor substrate, thereby defining the tunnel region therewith, and a tunnel insulating layer including at least one silicon nitride film is provided within the aperture.

Abstract: An electrically erasable and programmable non-volatile semiconductor having a selection transistor, a memory transistor, and a logic transistor. The selection transistor has a first gate insulating film of a first film thickness and is made operative by a gate voltage of about 20V. The memory transistor has a second gate insulating film comprising a first portion whose film thickness is the same as the first film thickness and a second portion of a second film thickness smaller than the first film thickness. The memory transistor also has an electrically floating gate arranged on the second gate insulating film. The logic transistor has a third gate insulating film of a third film thickness smaller than the first film thickness but larger than the second film thickness and is made operative by a gate voltage of about 5V. When the second film thickness is represented by A, the third film thickness by B, and the first film thickness by C, A:B:C=1:2.1:4.2.