Abstract: A demodulation timing generation circuit capable of generating correctly and with high precision a timing for demodulating a reception signal even under various kinds of reception conditions and a demodulation apparatus using the same, wherein AGC control and frequency offset correction are performed by the burst detector 109 and the amplification gain controller 111 using a synchronization training signal (burst signal) added to the head of the reception signal (packet), a detection window period is provided for cross-correlation detection to detect the peak of the cross-correlation in the detection window DW by the timing controller 110, and in the end (rear edge) of the window, data corresponding to the peak position is loaded in the counter 11003 for counting the OFDM symbol interval. Due to this, it is possible to set an optimal FFT timing irrespective of the condition of a channel.

Abstract: The present invention is applied to a portable personal computer or the like having a plurality of wireless communication means, for example, so as to provide a user with appropriate wireless communication means in a situation where a plurality of wireless communication means are available. According to the present invention, the wireless communication means is selectively used in accordance with an application program with reference to a communication management table in which at least wireless communication means allowed to be used is described with regard to respective application programs.

Abstract: An automatic gain control circuit able to perform high speed and correct level acquisition, able to prevent occurrence of error, and able to prevent a crash of the system, a method of same, and a demodulation apparatus, provided with an amplification gain controller 211 for outputting a gain control signal to an automatic gain control amplifier 201 so as to amplify the reception signal with the maximum value when receiving a burst detection starting use trigger signal, calculating a second gain based on a reception signal power value detected at a reception signal power monitor 202 when receiving a first burst synchronization detection signal from the burst detector, outputting the gain control signal to the automatic gain control amplifier 201 so as to amplify the reception signal with the second gain, receiving the digital reception signal amplified with the second gain and integrating the same to find the reception signal power value, calculating a third gain based on the found reception signal power value

Abstract: A carrier reproducing apparatus and method enabling stable operation even at a low S/N, wherein, when phase signals are locked and exceed a predetermined value, a tracking circuit generates a signal and an oscillation frequency of a signal output from a numerical control oscillation circuit is controlled so that the phase signals do not exceed the predetermined value and wherein a down sampling circuit and an interpolation circuit convert signals having a frequency of more than twice the symbol rate to signals having a frequency of twice the symbol rate.

Abstract: A carrier reproducing apparatus and method enabling stable operation even at a low S/N, wherein, when phase signals are locked and exceed a predetermined value, a tracking circuit generates a signal and an oscillation frequency of a signal output from a numerical control oscillation circuit is controlled so that the phase signals do not exceed the predetermined value and wherein a down sampling circuit and an interpolation circuit convert signals having a frequency of more than twice the symbol rate to signals having a frequency of twice the symbol rate.

Abstract: Upon the power-on, a digital signal processing circuit supplies an AGC signal to an AGC amplifier to squelch it substantially, thereby prohibiting an analog signal from being input to an A/D converter 6 via a DC level setting circuit. In this state, a DC level that is set by the DC level setting circuit is A/D-converted by the A/D converter and a resulting value is input to the digital signal processing circuit. The digital signal processing circuit calculates and stores, as a DC offset value, a difference between the received DC level and the center value of the dynamic range of the A/D converter. In a stationary state, the AGC amplifier is caused to operate normally and the offset value is subtracted from data that is supplied from the A/D converter. Resulting data is output from an output terminal.

Abstract: A demodulator and a demodulation method are designed so as to reduce the load of a CPU. A host CPU controls a digital demodulation circuit, an error correction circuit, a transport circuit and an MPEG decoder through a bus. The host CPU outputs a control signal to a format conversion circuit via a CPU interface when it instructs a tuner to perform tuning. The format conversion circuit converts the format of this control signal into a 3-wire format and outputs the converted signal to a frequency divider of the tuner.

Abstract: Survivor sequences information is supplied to a RAM 61-1 and a RAM 61-2 as an input Din. The RAM 61-1 and the RAM 61-2 perform an interleaving operation and store the survivor sequences information alternately in accordance with a clock CK1 and a clock CK2 differing in phase from the clock CK1 by half a period. The phases of the clock CK1 and the phase of the clock CK2 are delayed by half a period when a write operation is switched to a read operation with data being outputted at a selector 62 in an appropriate order accordingly. Traced-back data is then inputted from terminal A and terminal B to the selector 62 and outputted from a terminal X after one of these items of data has been selected at a prescribed timing.

Abstract: A video storage device capable of realizing a still image-holding mode. The storage device has a serial input-output configuration. A serial input register is connected with a memory array via a transfer gate circuit which selectively permits transfer of data from the serial input register to the memory array. An address counter is connected with the serial input register. In the still image-holding mode, the transfer gate circuit is disabled, and the memory array is accessed in response to counting operation of the address counter. The address counter acts also as a refreshing counter for refreshing the memory array.

Abstract: An arbitrate circuit prioritizes a plurality of competing request signals by utilizing a plurality of gate circuits to receive a corresponding plurality of request signals. The first gate circuit to receive a request signal passes the request signal and at the same time prevents the remaining gate circuits from passing any request signals until the request signal has completely passed through the first gate circuit.

Abstract: A serial access semiconductor memory device having a column redundant system employs a parallel-serial conversion circuit including a plurality of series connected flipflop circuits and a plurality of selectors provided between the flipflop circuit. At the selector associated unit the final stage of the flipflop circuits in the parallel-serial conversion circuit, defective data from a memory cell array are replaced to redundant data from the column redundant system without large scale circuitry and complicated control signals. An improved fuse ROM or an improved comparator is employed for the semiconductor memory device to control the switching from the defective data to redundant data. The fuse ROM employs a latch circuit for reducing stand-by current. The comparator employs a plurality of MOS transistors to compare effectively. The relation between the fuse ROM and the comparator provides a simplified circuit construction of an asynchronous multi-port device or a device having a plurality of memory blocks.