Patents by Inventor Masatake Katayama

Masatake Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6254933
    Abstract: A method of performing chemical vapor deposition which produces semiconductor crystalline thin films having small transition widths. The method involves the use of a cold-wall type reaction chamber that is equipped with a gas inlet at one end and a gas outlet at the other end and a semiconductor substrate support which supports a semiconductor substrate so that a main surface thereof is horizontal. A reactant gas is caused to flow horizontally through the reaction chamber to effect the growing of a crystalline thin film on the main surface of the semiconductor substrate. The semiconductor substrate is arranged within the reactor chamber within a distance W which is measured from a leading edge of the semiconductor substrate at a most upstream position along a direction toward the gas outlet where W indicates an internal width of the reaction chamber.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: July 3, 2001
    Assignee: Shin-Etsu Handotai, Ltd.
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 6048793
    Abstract: In a method and an appratus for a thin film growth on a semiconductor crystal substrate, impurities and contaminants absorbed on the inside wall of the reaction vessel are very harmful because these impurities and contaminants will deteriorate the quality of the thin film. A method and an apparatus by which the quantity of these impurities and contaminants absorbed on the inside wall of the reaction vessel can be restrained and removed easily are disclosed in this invention, wherein a semiconductor crystal substrate is mounted in the reaction vessel, and the wall of the reation vessel is cooled forcibly by a coolant while the substrate is under heating procedure to grow a thin film on the substrate by supplying the raw material gas into the reaction vessel. And the temperature of the wall of the reaction vessel during the procedure except the thin film growth is kept higher temperature than the temprature of the wall of the reaction vessel during the thin film growth procedure.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: April 11, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 6008128
    Abstract: A method for microscopically smoothing a surface of a wafer made of silicon single crystal having a low resistivity. In the method, a native oxide film grown on a surface of a wafer having polished by an ordinary mirror polishing process is removed at a temperature of less than 100.degree. C. with use of a mixture gas of HF and H.sub.2, and then an organic substance deposited thereon is removed at a temperature of less than 800.degree. C. with use of a mixture gas of HCl and H.sub.2. Re-growth of an oxide film is suppressed in a consistent H.sub.2 atmosphere, during which the wafer is substantially not varied in its surface roughness. Then the wafer is thermally treated in an H.sub.2 gas atmosphere at a temperature of not less than 800.degree. C. and less than 1000.degree. C.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: December 28, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Toru Otsuka, Masatake Katayama
  • Patent number: 5998281
    Abstract: Proposed is an improvement in the process for the preparation of an SOI wafer comprising the steps of: forming an oxidized surface film on the mirror-polished surface of a first mirror-polished semiconductor silicon wafer as the base wafer; forming a doped layer with a dopant in a high concentration on the mirror-polished surface of a second mirror-polished semiconductor silicon wafer as the bond wafer; bringing the base wafer and the bond wafer into contact each with the other at the oxidized surface film and the doped layer; and subjecting the thus contacted semiconductor silicon wafers to a heat treatment to effect integral bonding thereof into a precursor of an SOI wafer. The improvement of the invention is accomplished by polishing the surface of the doped layer on the bond wafer before the base wafer and the bond wafer are joined by contacting at the oxidized surface film and the doped layer so that a great improvement can be obtained in the bonding strength between layers.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: December 7, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Kiyoshi Mitani, Masatake Katayama
  • Patent number: 5938840
    Abstract: In the formation of a thin film on the surface of a semiconductor crystal substrate by using a horizontal type vapor phase growth apparatus, the distribution of the thickness and resistivity of the thin film can be properly obtained by adjusting the concentration distribution of the raw material gas in the mixture gas in the width direction of the reaction vessel over the substrate surface. And in the reaction vessel, carrier gas is supplied from the position close to the transfer port of the substrate, and raw material gas is supplied from the position located in the downstream side of a vortex generation region caused by the flow of the carrier gas.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: August 17, 1999
    Assignee: Shin-Etsu Handotai, Co., Ltd
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 5804494
    Abstract: A method of fabricating a bonded wafer which is capable of reducing the concentrations of impurities, and more particularly the boron concentration, at the interface of bonding in the bonded wafer, wherein first and second wafers to be bonded are finish-cleaned, then the wafers are temporarily stored in a closed box so as to isolate the wafers from clean-room air, thereafter the first and second wafers are superposed in a clean atmosphere which is held out of direct contact with clean-room air, and finally the superposed first and second wafers are bonded together by a heat-treatment.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: September 8, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Masatake Katayama, Kazushi Nakazawa
  • Patent number: 5759426
    Abstract: A silicon nitride layer 12b is thermally grown on the topmost surface of the heat treatment jig 12 composed of silicon or silicon carbide in a nitrogen ambience. The silicon nitride layer 12b is thermally grown in a nitrogen ambience in the temperature range of 1,100.degree. C.-1,300.degree. C. It is desirable to remove slightly the surface of the jig by, for example, hydrogen etching before thermally growing the silicon nitride layer 12b. After the etching, a silicon oxide layer can be thermally grown on the jig surface in an oxygen ambience before thermally growing the silicon nitride layer 12b.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: June 2, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Kazuo Mamada, Yuichi Matsumoto, Satoshi Oka, Masatake Katayama
  • Patent number: 5755878
    Abstract: In the formation of a thin film on the surface of a semiconductor crystal substrate by using a horizontal type vapor phase growth apparatus, the distribution of the thickness and resistivity of the thin film can be properly obtained by adjusting the concentration distribution of the raw material gas in the mixture gas in the width direction of the reaction vessel over the substrate surface. And in the reaction vessel, carrier gas is supplied from the position close to the transfer port of the substrate, and raw material gas is supplied from the position located in the downstream side of a vortex generation region caused by the flow of the carrier gas.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: May 26, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 5749974
    Abstract: A reactor for chemical vapor deposition which is capable of producing semiconductor crystalline thin films having small transition widths. The reactor includes a cold-wall type reaction chamber that is equipped with a gas inlet at one end and a gas outlet at the other end and a semiconductor substrate support which supports a semiconductor substrate so that a main surface thereof is horizontal. A reactant gas is caused to flow horizontally through the reaction chamber to effect the growing of a crystalline thin film on the main surface of the semiconductor substrate. The semiconductor substrate is arranged within the reactor chamber within a distance W which is measured from a leading edge of the semiconductor substrate at a most upstream position along a direction toward the gas outlet where W indicates an internal width of the reaction chamber.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: May 12, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Masanori Mayuzumi, Naoto Tate, Masatake Katayama
  • Patent number: 5718762
    Abstract: A method for vapor-phase growth which allows an epiwafer of a smooth surface free from microroughness to be produced is provided. This method comprises a step of heating up a silicon single crystal substrate in an ambience of an inert gas started at a temperature of less than 800.degree. C. and a step of removing a native oxide film formed on the surface of the silicon single crystal substrate by etching with hydrogen gas in an ambience of hydrogen gas at a temperature of not less than 950.degree. C. and not more than 1190.degree. C. prior to the vapor-phase growth.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: February 17, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Naoto Tate, Masanori Mayuzumi, Hitoshi Tsunoda, Masatake Katayama
  • Patent number: 5696034
    Abstract: A method for producing a semiconductor substrate in which no autodoping occurs and slip dislocations in the substrate are reduced. The method involves forming a silicon nitride film on the backside of an n.sup.- -silicon substrate, epitaxially growing an n.sup.+ -buffer layer and a p.sup.+ -layer on the front side of the n.sup.- -silicon substrate, and decreasing the thickness of the n.sup.- -silicon substrate from the backside.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: December 9, 1997
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masatake Katayama, Isao Moroga, Isao Shirai, Youichi Kumaki, Akio Kasahara
  • Patent number: 5650353
    Abstract: SOI (silicon-on-insulator) substrates are efficiently produced by a method which comprises superposing and bonding at least three single crystal silicon wafers through the medium of a SiO.sub.2 film formed on the surface of each of the wafers and cutting the bonded wafers along planes perpendicular to the direction of superposition thereof. The cutting can be infallibly attained with high dimensional accuracy without entailing such adverse phenomena as the vibration of the blade of a cutting tool by providing at the portions destined to be cut the grooves for guiding the blade of the cutting tool in advance of the cutting work.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: July 22, 1997
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Katsuo Yoshizawa, Tsutomu Sato, Kiyoshi Mitani, Masatake Katayama
  • Patent number: 5538904
    Abstract: A method of estimating the amount of boron on the surface of silicone samples in which a plurality of reference samples shallowly ion-implanted with boron in different dosages are prepared and heat-treated under the same conditions of temperature and time as are used in a bonding heat treatment to obtain the bonded wafer, thereafter, the boron profile in the direction of the depth of the bonding interface in each reference sample is measured using a SIMS and compared with an actual boron profile at the bonding interface of a bonded wafer to be estimated so as to determine one reference sample whose boron profile is equivalent to the actual boron profile of the bonded wafer to be estimated, and finally a dosage of boron in the determined reference sample is estimated by convertion to be a surface density of boron presenting at the bonding interface of the bonded wafer to be estimated at an initial stage prior to the bonding heat treatment of the bonded wafer to be estimated.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: July 23, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Masatake Katayama, Kazushi Nakazawa
  • Patent number: 5514235
    Abstract: A method is disclosed for obtaining bonded wafers of SOI type, where impurity redistribution in the bulk of the wafers is suppressed and the bonding strength between the wafers is substantially higher compared with that in the prior art. This is accomplished by forming a thermally grown oxide layer on the surface of the thinner one(bond wafer) of two monocrystalline silicon wafers having thicknesses different from each other by more than 50 .mu.m; then superposing the thinner wafer onto the other thicker wafer(base wafer); and finally conducting at least two heat treatments of the wafers at temperatures selected in the range of under 900.degree. C. for a period of time selected in the range of from 0.5 min. to 120 min.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: May 7, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Masatake Katayama
  • Patent number: 5478408
    Abstract: There is provided an SOI (Silicon On Insulator) substrate having a thick SOI layer, where crystallographic defects mainly consisting of OSFs (Oxidation Induced Stacking Fault) are practically prevented from occurrence in the SOI layer, according to the present invention.The manufacturing method for the SOI substrate according to the present invention comprises the following steps of: the silicon oxide film being formed by thermal oxidation on the surface of a first silicon wafer having a concentration of interstitial oxygen under 16 ppma (per JEIDA Standard); the first silicon wafer being superimposed on a second silicon wafer, which is a support for supporting the first silicon wafer, with the silicon oxide film sandwiched therebetween; then the superimposed wafers being heat-treated so as to obtain a bonded wafer; and further the bulk of the first silicon wafer of the bonded wafer being reduced by grinding and then polishing so as to obtain the SOI substrate with the SOI layer of more than 5 .mu.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: December 26, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Masatake Katayama, Kazushi Nakazawa
  • Patent number: 5427052
    Abstract: A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: June 27, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Nakano, Masatake Katayama, Takao Abe
  • Patent number: 5393370
    Abstract: To provide a method of making a SOI film having a more uniform thickness in a SOI substrate which makes it possible to keep the variance at .+-.0.3 micrometers or less throughout the entire surface of the substrate, even for SOI substrates with a SOI film thickness between 1 micrometer and 10 micrometers. The surface of a SOI substrate is divided into a plurality of sections, then the SOI film thickness is measured for each section Wi (i=1-n) by means of the spectral interference method using an optical fiber cable, and, simultaneously, the SOI film is etched down to a prescribed thickness by a dry etching device, and thus a desired value and a variance (.+-.0.3 micrometers) of the SOI film thickness is obtained.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: February 28, 1995
    Assignee: Shin-Etsu Handotai Kabushiki Kaisha
    Inventors: Yutaka Ohta, Masatake Katayama, Isao Moroga
  • Patent number: 5376215
    Abstract: A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: December 27, 1994
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Nakano, Masatake Katayama, Takao Abe
  • Patent number: 5336634
    Abstract: A dielectrically isolated substrate is comprised of a single-crystal silicon substrate or bond substrate and a single-crystal silicon substrate or base substrate bonded together into a composite structure. The bond substrate has a (110) plane as a main crystal plane and is provided with vertically walled moats and substantially squared islands positioned adjacent to the moats. The moats and islands result from anisotropic etching using a specific mask pattern. Also disclosed is a process for producing the composite structure.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: August 9, 1994
    Assignee: Shin-Etsu Handotui Co., Ltd.
    Inventors: Masatake Katayama, Makoto Sato, Yutaka Ohta, Mitsuru Sugita, Konomu Ohki
  • Patent number: 5240883
    Abstract: A thin Silicon film On Insulator (SOI) material fabricating method which is capable of providing a very high thickness uniformity of the silicon film, a process simplification and a considerable reduction of processing cost is disclosed, in which a silicon oxide film is formed on one or both of a p-type silicon bond wafer and a silicon base wafer, then the two wafers are bonded together through the silicon oxide film, subsequently a fixed positive charge is induced in the silicon oxide film to form a n-type inversion layer in the p-type silicon bond wafer adjacent to an interface between the p-type silicon bond wafer and the silicon oxide film layer, and thereafter a chemical etching is effected while applying a positive voltage to the p-type silicon bond wafer so that an etch-stop is made at an interface between a depletion layer including the n-type inversion layer and the p-type layer.
    Type: Grant
    Filed: February 25, 1992
    Date of Patent: August 31, 1993
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takao Abe, Masatake Katayama, Akio Kanai, Konomu Ohki, Masatake Nakano