Abstract: A semiconductor device has a plurality of interconnect layers each including a plurality of interconnect lines. The semiconductor device includes a dielectric film (HDP film) formed by means of high density plasma-enhanced CVD and including an edge formed on the side surface of the topmost-layer interconnect lines, a silicon oxide film formed by modifying a SOG film on the HDP film between adjacent two of the topmost-layer interconnect lines in the element forming region, and a passivation film formed to cover the HDP film and the topmost-layer interconnect lines.

Abstract: In order to improve the yield by suppressing peeling or the like of an accessory pattern when dicing, there include: a substrate on which an element forming region and a scribe line region formed around the element forming region are provided; an accessory pattern formed on the scribe line region; a protective film covering the element forming region on the substrate; and supporting films located in the opening formed in the scribe line region and supporting the accessory pattern locally. Each of the supporting film is formed as a continuation of the protective film, and has a function of supporting an edge of the accessory pattern while avoiding a part along which the accessory pattern is diced with a dicing blade.

Abstract: A semiconductor device has a plurality of interconnect layers each including a plurality of interconnect lines. The semiconductor device includes a dielectric film (HDP film) formed by means of high density plasma-enhanced CVD and including an edge formed on the side surface of the topmost-layer interconnect lines, a silicon oxide film formed by modifying a SOG film on the HDP film between adjacent two of the topmost-layer interconnect lines in the element forming region, and a passivation film formed to cover the HDP film and the topmost-layer interconnect lines.

Abstract: In order to improve the yield by suppressing peeling or the like of an accessory pattern when dicing, there include: a substrate on which an element forming region and a scribe line region formed around the element forming region are provided; an accessory pattern formed on the scribe line region; a protective film covering the element forming region on the substrate; and supporting films located in the opening formed in the scribe line region and supporting the accessory pattern locally. Each of the supporting film is formed as a continuation of the protective film, and has a function of supporting an edge of the accessory pattern while avoiding a part along which the accessory pattern is diced with a dicing blade.

Abstract: A semiconductor device and method of manufacture are provided wherein a contact hole can be formed with increased contact area while maintaining sufficient isolation between an electroconductive layer deposited in the contact hole and an adjacent wire. According to one embodiment (100), a double-layered side-wall insulating layer can be formed within a contact hole (116). The upper (second) side-wall insulating layer (120) can be etched back to expose part of the lower (first) side-wall insulating layer (118) formed in the bottom of the contact hole (116). Subsequently, the exposed portion of the first side-wall insulating layer (118) can be subject to a wet etch to remove the portion of the first side-wall insulating layer (118) at the bottom of the contact hole (116).

Abstract: A semiconductor device and method of manufacture are provided wherein a contact hole can be formed with increased contact area while maintaining sufficient isolation between an electroconductive layer deposited in the contact hole and an adjacent wire. According to one embodiment (100), a double-layered side-wall insulating layer can be formed within a contact hole (116). The upper (second) side-wall insulating layer (120) can be etched back to expose part of the lower (first) side-wall insulating layer (118) formed in the bottom of the contact hole (116). Subsequently, the exposed portion of the first side-wall insulating layer (118) can be subject to a wet etch to remove the portion of the first side-wall insulating layer (118) at the bottom of the contact hole (116).

Abstract: A semiconductor device and method of manufacture are provided wherein a contact hole can be formed with increased contact area while maintaining sufficient isolation between an electroconductive layer deposited in the contact hole and an adjacent wire. According to one embodiment (100), a double-layered side-wall insulating layer can be formed within a contact hole (116). The upper (second) side-wall insulating layer (120) can be etched back to expose part of the lower (first) side-wall insulating layer (118) formed in the bottom of the contact hole (116). Subsequently, the exposed portion of the first side-wall insulating layer (118) can be subject to a wet etch to remove the portion of the first side-wall insulating layer (118) at the bottom of the contact hole (116).

Abstract: According a method of manufacturing a semiconductor device, a polysilicon layer is formed on a semiconductor substrate and is patterned, thereby forming a storage electrode and plate electrode in a memory cell region and leaving the polysilicon layer in an aligning mark formation region. An interlevel insulating film is formed on the semiconductor substrate including the storage electrode, plate electrode, and polysilicon layer. An upper interconnection layer is formed on the polysilicon layer and is patterned, thereby forming an upper interconnection layer in the memory cell region and an aligning mark in the aligning mark formation region. An interlevel insulating film is formed on the upper interconnection layer and aligning mark and is etched back, thereby planarizing the memory cell region and aligning mark formation region and removing the interlevel insulating film on the aligning mark.

Abstract: A method of manufacturing a semiconductor device that can limit etch damage is disclosed. According to one embodiment, isolation regions (102) may be formed in a substrate (101). A word line (103) may be formed in a first region. A protective film (105) may be formed over the first region and a second region. A protective film (105) may then be etched from the second region but retained in the first region. A sidewall layer (107) may then be formed over the first and second regions, and etched to form sidewalls (107-a). The protective film (105-a) over the first region can reduce etch damage. Further, because a protective film (105-a) can be thinner than a sidewall layer (107), a resulting step height between the first region and second region may be reduced. Reductions in such a step height can result in better focus margins for subsequent photolithographic steps.

Abstract: A method of forming a side wall contact on a side wall of a contact hole in an inter-layer insulator structure by an etch-back process The method includes forming a first insulation film on a top insulation layer of the inter-layer insulator structure, forming a second insulation film to extend on the side wall and a bottom of the contact hole as well as on a surface of the first insulation film. The first insulation film has a higher etching selectivity than the top insulation layer of the inter-layer insulator structure and the second insulation film has a lower etching selectivity than the top insulation layer of the inter-layer insulator structure. The second insulation film is lower in etching selectivity than the first insulation film.

Abstract: A semiconductor device and a producing method thereof in which a step or difference in height between a first resist trace for forming a wiring pattern within a production region and a second resist trace for forming an accessory pattern such as an alignment mark is largely reduced. The second resist trace is formed on a projection part. The projection part is composed of insulating layers and conductive layers, which are intentionally left, corresponding to first and second interlayer insulating films, a storage electrode and a plate electrode formed in the wiring pattern within the production region and further of a second upper wiring and a ground film of a conventional device. With the largely reduced height difference between the two patterns, a focusing adjustment between the two patterns can be improved and the resist shapes can be formed with high accuracy.

Abstract: The present invention provides a method of forming a side wall contact on a side wall of a contact hole in an inter-layer insulator structure by an etch-back process.

Abstract: A semiconductor device manufacturing method and a semiconductor device whereby alignment accuracy of a lower-layer pattern and an upper-layer pattern in a photolithography process may be improved. There are provided a pair of box marks for measuring the relative position between a lower-layer pattern and an upper-layer pattern of a semiconductor device in a box mark formation region. Since one box mark of the pair of box marks includes an opening groove 9-a formed on an interlayer insulating film 7 and a slit 9-b with a rectangular shape having a center roughly the same as the center of the opening groove 9-a, while the other box mark of the pair of box marks is an alignment mark 11-a formed on the opening groove, it is possible to suppress the change in shape of the edge part of the opening groove 9-a to a minimum even if reflow occurs again in the interlayer insulating film 7.

Abstract: According a method of manufacturing a semiconductor device, a polysilicon layer is formed on a semiconductor substrate and is patterned, thereby forming a storage electrode and plate electrode in a memory cell region and leaving the polysilicon layer in an aligning mark formation region. An interlevel insulating film is formed on the semiconductor substrate including the storage electrode, plate electrode, and polysilicon layer. An upper interconnection layer is formed on the polysilicon layer and is patterned, thereby forming an upper interconnection layer in the memory cell region and an aligning mark in the aligning mark formation region. An interlevel insulating film is formed on the upper interconnection layer and aligning mark and is etched back, thereby planarizing the memory cell region and aligning mark formation region and removing the interlevel insulating film on the aligning mark.

Abstract: A semiconductor memory device comprises a capacitor having a double-cylinder structure wherein a storage electrode has two cylindrical portions each opposing an upper electrode, with a capacitor insulating film disposed therebetween. The outer cylindrical portion has a smaller length than the inner cylindrical portion, thereby allowing the capacitor to have a smaller height as viewed toward the outer direction. The boundary between the memory array region and peripheral region has a moderate step to thereby prevent breakage of an overlying interconnection and reduce etching residue.