Patents by Inventor Masateru Koide
Masateru Koide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11317520Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.Type: GrantFiled: October 17, 2018Date of Patent: April 26, 2022Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITEDInventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki Akahoshi, Masateru Koide, Manabu Watanabe, Seigo Yamawaki, Kei Fukui
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Patent number: 10396020Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.Type: GrantFiled: April 19, 2018Date of Patent: August 27, 2019Assignee: FUJITSU LIMITEDInventors: Kei Fukui, Youichi Hoshikawa, Hiromitsu Kobayashi, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, Manabu Watanabe, Daisuke Mizutani, Tomoyuki Akahoshi
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Publication number: 20190053385Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Applicant: FUJITSU LIMITEDInventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki AKAHOSHI, Masateru Koide, MANABU WATANABE, Seigo Yamawaki, Kei FUKUI
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Patent number: 10181437Abstract: A package substrate includes a substrate, a first connection terminal mounted over the substrate, the first connection terminal including a first land and a second land on the substrate, a first solder resist surrounding the first land and the second land, and a first solder ball formed straddling the first land and the second land; and a second connection terminal which is mounted over the substrate and disposed adjacent to the first connection terminal, the second connection terminal including a third land and a fourth land on the substrate, a second solder resist surrounding the third land and the fourth land, and a second solder ball formed straddling the third land and the fourth land.Type: GrantFiled: June 7, 2018Date of Patent: January 15, 2019Assignee: Fujitsu LimitedInventors: Manabu Watanabe, Kenji Fukuzono, Yuki Hoshino, Masateru Koide
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Publication number: 20180358289Abstract: A package substrate includes a substrate, a first connection terminal mounted over the substrate, the first connection terminal including a first land and a second land on the substrate, a first solder resist surrounding the first land and the second land, and a first solder ball formed straddling the first land and the second land; and a second connection terminal which is mounted over the substrate and disposed adjacent to the first connection terminal, the second connection terminal including a third land and a fourth land on the substrate, a second solder resist surrounding the third land and the fourth land, and a second solder ball formed straddling the third land and the fourth land.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Applicant: FUJITSU LIMITEDInventors: MANABU WATANABE, KENJI FUKUZONO, Yuki Hoshino, Masateru Koide
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Publication number: 20180315687Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.Type: ApplicationFiled: April 19, 2018Publication date: November 1, 2018Applicant: FUJITSU LIMITEDInventors: Kei FUKUI, Youichi Hoshikawa, Hiromitsu KOBAYASHI, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, MANABU WATANABE, Daisuke Mizutani, Tomoyuki AKAHOSHI
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Patent number: 9699887Abstract: A circuit board includes a substrate, a first ground electrode group, and a first pair of signal electrodes. The first ground electrode group includes a plurality of first ground electrodes, where each of the plurality of the first ground electrodes is disposed at a corresponding one of vertexes of a first rectangular area in a surface of the substrate. the first pair of signal electrodes is disposed in the first rectangular area and is arranged in a first direction parallel to a side of the first rectangular area.Type: GrantFiled: March 7, 2014Date of Patent: July 4, 2017Assignee: FUJITSU LIMITEDInventors: Daisuke Mizutani, Kenichi Kawai, Takahito Takemoto, Masateru Koide
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Patent number: 9515005Abstract: A package mounting structure includes: a first substrate having wiring; a second substrate having wiring; at least one cooling unit having a first face and a second face different from the first face; at least one power supply unit that is mounted on the first substrate and is joined to the first face of the cooling unit; and at least one electronic component that is mounted on the second substrate and is joined to the second face of the cooling unit, wherein the power supply unit supplies power to the electronic component through the wiring of the first substrate, the cooling unit, and the wiring of the second substrate.Type: GrantFiled: May 5, 2014Date of Patent: December 6, 2016Assignee: FUJITSU LIMITEDInventors: Shunji Baba, Masateru Koide, Manabu Watanabe, Takashi Kanda, Kenji Fukuzono, Yuki Hoshino, Makoto Suwada
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Publication number: 20140376187Abstract: A package mounting structure includes: a first substrate having wiring; a second substrate having wiring; at least one cooling unit having a first face and a second face different from the first face; at least one power supply unit that is mounted on the first substrate and is joined to the first face of the cooling unit; and at least one electronic component that is mounted on the second substrate and is joined to the second face of the cooling unit, wherein the power supply unit supplies power to the electronic component through the wiring of the first substrate, the cooling unit, and the wiring of the second substrate.Type: ApplicationFiled: May 5, 2014Publication date: December 25, 2014Applicant: FUJITSU LIMITEDInventors: Shunji Baba, Masateru Koide, Manabu Watanabe, Takashi Kanda, Kenji Fukuzono, Yuki Hoshino, Makoto Suwada
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Patent number: 8866270Abstract: A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate.Type: GrantFiled: March 11, 2014Date of Patent: October 21, 2014Assignee: Fujitsu LimitedInventors: Manabu Watanabe, Masateru Koide, Kenji Fukuzono, Takashi Kanda
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Publication number: 20140293566Abstract: A circuit board includes a substrate, a first ground electrode group, and a first pair of signal electrodes. The first ground electrode group includes a plurality of first ground electrodes, where each of the plurality of the first ground electrodes is disposed at a corresponding one of vertexes of a first rectangular area in a surface of the substrate. the first pair of signal electrodes is disposed in the first rectangular area and is arranged in a first direction parallel to a side of the first rectangular area.Type: ApplicationFiled: March 7, 2014Publication date: October 2, 2014Applicant: FUJITSU LIMITEDInventors: Daisuke Mizutani, Kenichi Kawai, Takahito Takemoto, Masateru Koide
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Patent number: 8811031Abstract: A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that ? is a coefficient of thermal expansion of the wiring board, ? is a coefficient of thermal expansion of the base substrate, and ? is a coefficient of thermal expansion of the adhesive layer, the relationship ?<?<? is satisfied.Type: GrantFiled: August 9, 2010Date of Patent: August 19, 2014Assignee: Fujitsu LimitedInventors: Masateru Koide, Daisuke Mizutani
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Publication number: 20140193953Abstract: A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: FUJITSU LIMITEDInventors: Manabu WATANABE, Masateru KOIDE, Kenji FUKUZONO, Takashi KANDA
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Patent number: 8740047Abstract: A method of manufacturing an electronic apparatus including a first and a second components, includes: forming a first solder bump on one of the first component and the second component; forming a second solder bump on the other one of the first component and the second component; bringing the first solder bump into contact with the second solder bump at a temperature higher than the liquidus temperature of any of the first and the second solder bumps such that the first and the second solder bumps are fused together to form a solder joint of an alloy having a lower liquidus temperature than any of the first and the second solder bumps; and solidifying the solder joint between the first and the second component.Type: GrantFiled: September 11, 2013Date of Patent: June 3, 2014Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Toshiya Akamatsu, Masateru Koide
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Patent number: 8716839Abstract: A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate.Type: GrantFiled: May 17, 2013Date of Patent: May 6, 2014Assignee: Fujitsu LimitedInventors: Manabu Watanabe, Masateru Koide, Kenji Fukuzono, Takashi Kanda
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Publication number: 20140008114Abstract: A method of manufacturing an electronic apparatus including a first and a second components, includes: forming a first solder bump on one of the first component and the second component; forming a second solder bump on the other one of the first component and the second component; bringing the first solder bump into contact with the second solder bump at a temperature higher than the liquidus temperature of any of the first and the second solder bumps such that the first and the second solder bumps are fused together to form a solder joint of an alloy having a lower liquidus temperature than any of the first and the second solder bumps; and solidifying the solder joint between the first and the second component.Type: ApplicationFiled: September 11, 2013Publication date: January 9, 2014Applicant: FUJITSU LIMITEDInventors: Seiki Sakuyama, Toshiya Akamatsu, Masateru Koide
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Publication number: 20130341767Abstract: A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate.Type: ApplicationFiled: May 17, 2013Publication date: December 26, 2013Applicant: FUJITSU LIMITEDInventors: Manabu WATANABE, Masateru KOIDE, Kenji FUKUZONO, Takashi KANDA
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Patent number: 8556157Abstract: A method of manufacturing an electronic apparatus including a first and a second components, includes: forming a first solder bump on one of the first component and the second component; forming a second solder bump on the other one of the first component and the second component; bringing the first solder bump into contact with the second solder bump at a temperature higher than the liquidus temperature of any of the first and the second solder bumps such that the first and the second solder bumps are fused together to form a solder joint of an alloy having a lower liquidus temperature than any of the first and the second solder bumps; and solidifying the solder joint between the first and the second component.Type: GrantFiled: May 23, 2011Date of Patent: October 15, 2013Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Toshiya Akamatsu, Masateru Koide
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Patent number: 8546187Abstract: A method of manufacturing a multi-chip module includes: securing a plurality of chips on a surface of a flat-shaped member through a solder bump; connecting the plurality of chips with each other by a bonding wire, at surfaces, opposite to the flat-shaped member side, of the plurality of chips; and electrically connecting the plurality of chips with a board, at the surfaces, opposite to the flat-shaped member side, of the plurality of chips.Type: GrantFiled: August 17, 2010Date of Patent: October 1, 2013Assignee: Fujitsu LimitedInventors: Masateru Koide, Daisuke Mizutani
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Patent number: 8446020Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.Type: GrantFiled: October 12, 2010Date of Patent: May 21, 2013Assignees: Fujitsu Limited, Fujitsu Semiconductor LimitedInventors: Masateru Koide, Daisuke Mizutani, Aiichiro Inoue, Hideo Yamashita, Iwao Yamazaki, Masayuki Kato, Seiji Ueno, Kazuyuki Imamura