Abstract: A semi-conductor storing apparatus is provided, which comprises plural storing units, each having a line buffer including plural flip-flop circuits and a clock supplying circuit for supplying a clock to the plural flip-flop circuits, a clock-controlling unit, which controls on/off operation of the clock supplying circuit to decide whether to output a clock, a selecting unit, which selects one from among outputs from the plural storing units, and an unit-controlling unit, which controls the operations of the clock-controlling unit and the selecting unit.

Abstract: A power consumption of a semiconductor integrated circuit is reduced. A semiconductor integrated circuit comprises a first path P1 for performing data processing in a data processing circuit and a second path P2 for bypassing the data processing circuit or for performing data processing in a simplified circuit. The semiconductor integrated circuit exclusively selects the first path and the second path depending on an operational mode, and stops a data input into a path that is not selected, resulting in a reduction of the power consumption.

Abstract: In a microcomputer provided with a program storing device for storing instruction codes and a micro-processor for reading and executing the instruction codes stored in the program storing device, the program storing device have plural memories for storing instruction codes, an output unit for receiving plural pieces of data output from the plural memories, and selecting and outputs one of the plural pieces of data received from the plural memories, a selecting unit for receiving address data sent from the micro-processor to select one of the plural memories, an activating unit for activating the memory selected by the selecting unit, and a controlling unit for controlling the output unit to output data of the memory activated by the activating unit.

Abstract: A semi-conductor storing apparatus is provided, which comprises plural storing units, each having a line buffer including plural flip-flop circuits and a clock supplying circuit for supplying a clock to the plural flip-flop circuits, a clock-controlling unit, which controls on/off operation of the clock supplying circuit to decide whether to output a clock, a selecting unit, which selects one from among outputs from the plural storing units, and an unit-controlling unit, which controls the operations of the clock-controlling unit and the selecting unit.

Abstract: A power consumption of a semiconductor integrated circuit is reduced. A semiconductor integrated circuit comprises a first path P1 for performing data processing in a data processing circuit and a second path P2 for bypassing the data processing circuit or for performing data processing in a simplified circuit. The semiconductor integrated circuit exclusively selects the first path and the second path depending on an operational mode, and stops a data input into a path that is not selected, resulting in a reduction of the power consumption.

Abstract: A semiconductor circuit design supporting method includes: reading Register Transfer Level (RTL) description circuit data; generating an equivalent circuit corresponding to the RTL description circuit data; extracting a plurality of arithmetic components included in the generated equivalent circuit; clustering some of the extracted arithmetic components as a single arithmetic component, wherein no storage element exists between said some of the extracted arithmetic components; reading a timing constraint on the RTL description circuit data; tracing an exception path of the RTL description circuit data when the timing constraint includes a timing exception; determining whether or not the timing exception is set for input pins of said some of the arithmetic components which are clustered as the single arithmetic component, based on the traced exception path of the RTL description circuit data; and separating a arithmetic component for which the timing exception is set, from said some of the arithmetic component

Abstract: When driven in an all-pixel read mode, a CCD outputs, with each horizontal sync timing signal, captured image signals including signal charges arranged in a different order from that in which the pixels are actually arranged on a photosensitive surface of the CCD. During this time, the respective pixel signals are digitized sequentially by an A/D converter to corresponding image data, which are then temporarily stored in units of a line in a line buffer via a data distributor. In this case, an address generator generates, for the respective image data, write addresses to store the respective image data in the line buffer in the same order as the pixels of the photosensitive surface are actually arranged. In accordance with these write addresses, the data distributor distributes the respective image data to appropriate addresses in the line buffer, thereby storing the image data there.

Abstract: When driven in an all-pixel read mode, a CCD outputs, with each horizontal sync timing signal, captured image signals including signal charges arranged in a different order from that in which the pixels are actually arranged on a photosensitive surface of the CCD. During this time, the respective pixel signals are digitized sequentially by an A/D converter to corresponding image data, which are then temporarily stored in units of a line in a line buffer via a data distributor. In this case, an address generator generates, for the respective image data, write addresses to store the respective image data in the line buffer in the same order as the pixels of the photosensitive surface are actually arranged. In accordance with these write addresses, the data distributor distributes the respective image data to appropriate addresses in the line buffer, thereby storing the image data there.

Abstract: When driven in an all-pixel read mode, a CCD (1) outputs, with each horizontal sync timing signal, captured image signals including signal charges arranged in a different order from that in which the pixels are actually arranged on a photosensitive surface of the CCD. During this time, the respective pixel signals are digitized sequentially by an A/D converter (5) to corresponding image data, which are then temporarily stored in units of a line in a line buffer (7) via a data distributor (6). In this case, an address generator (8) generates, for the respective image data, write addresses to store the respective image data in the line buffer (7) in the same order as the pixels of the photosensitive surface are actually arranged. In accordance with these write addresses, the data distributor (6) distributes the respective image data to appropriate addresses in the line buffer (7), thereby storing the image data there (FIG. 1).

Abstract: When driven in an all-pixel read mode, a CCD (1) outputs, with each horizontal sync timing signal, captured image signals including signal charges arranged in a different order from that in which the pixels are actually arranged on a photosensitive surface of the CCD. During this time, the respective pixel signals are digitized sequentially by an A/D converter (5) to corresponding image data, which are then temporarily stored in units of a line in a line buffer (7) via a data distributor (6). In this case, an address generator (8) generates, for the respective image data, write addresses to store the respective image data in the line buffer (7) in the same order as the pixels of the photosensitive surface are actually arranged. In accordance with these write addresses, the data distributor (6) distributes the respective image data to appropriate addresses in the line buffer (7), thereby storing the image data there (FIG. 1).

Abstract: At the start of driving a stepping motor, a CPU sets the switching widths of the first through eighth states in a pulse width setting register, sets the switching counts of the first through eighth states in a pulse switching count register, and sets the start of driving the stepping motor in a driving start register. A latch then outputs an excitation pulse, and the stepping motor is accelerated, driven at a constant speed, decelerated, and stopped. By setting the switching widths and switching counts of the first through eighth states at the start of driving and setting the start of driving, the CPU need not control the stepping motor, reducing the process burden on the CPU.

Abstract: At the start of driving a stepping motor, a CPU sets the switching widths of the first through eighth states in a pulse width setting register, sets the switching counts of the first through eighth states in a pulse switching count register, and sets the start of driving the stepping motor in a driving start register. A latch then outputs an excitation pulse, and the stepping motor is accelerated, driven at a constant speed, decelerated, and stopped. By setting the switching widths and switching counts of the first through eighth states at the start of driving and setting the start of driving, the CPU need not control the stepping motor, reducing the process burden on the CPU.