Patents by Inventor Masato Ariyama

Masato Ariyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116227
    Abstract: A work holding mechanism includes a body part having a three-dimensional shape including at least a recess or a protrusion, and an adsorption part for holding a work by adsorbing the work onto the body part in conformity to the three-dimensional shape of the recess or the protrusion provided in the body part. The work is held by being adsorbed in conformity to the three-dimensional shape of the body part, and, therefore, the amount of usage of the work in a work molding system can be reduced as compared with when the work is held so as to have a flat shape.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: Dai Nippon Printing Co., LTD.
    Inventors: Kohei Ishizuka, Taisuke Uematsu, Takashi Konno, Hiroyuki Atake, Yoshiyuki Meiki, Minoru Ariyama, Masato Idegami
  • Publication number: 20170344688
    Abstract: A processor of an information processing apparatus displays a first component in a state in which a first terminal of the first component is located on a second terminal of a second component. The processor displays, along a designated route, a first wiring pattern for connecting the second terminal to the first terminal and moves the first component to a first distal end of the first wiring pattern. The processor determines whether a pattern area of the first wiring pattern or a component area of the first component which is placed at a second distal end of the designated route overlaps any of first areas of already placed components or second areas of already wired wiring patterns. The processor finalizes placement of the first component and the first wiring pattern upon determining that the pattern area and the component area overlap none of the first areas and the second areas.
    Type: Application
    Filed: April 5, 2017
    Publication date: November 30, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Kazuhiro SAKAI, Masato ARIYAMA, Kenichi NISHIMURA, Akira MIMURA, Yusuke KIMURA
  • Publication number: 20160246293
    Abstract: In the present case, when one component of a plurality of components is arranged, an interference state between a first check region set to the one component and a second check region set to an arranged component near the one component. If the checked interference state satisfies predetermined conditions, an arrangement position of the one component is determined by permitting the interference state. Then, the first check region and the second check region are combined and the combined check region is used as one check region set to the one component and the arranged component. Accordingly, the arrangement position of a component to be arranged can be determined by considering arrangements of a plurality of components therearound on a board.
    Type: Application
    Filed: January 6, 2016
    Publication date: August 25, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Kazuhiro Sakai, Masato Ariyama, AKIRA MIMURA, Yusuke Kimura
  • Patent number: 9261875
    Abstract: A design-support-apparatus includes a storage unit that stores mounting information on an order of manufacturing processes, first-region-information indicating a region to be secured in mounting of each component on the substrate, second-region-information indicating a region occupied when each component is mounted on the substrate, a discrimination unit configured to determine a before-and-after relationship between manufacturing processes of mounting a first-component and a second-component that are arranged on the substrate, an acquisition unit configured to acquire the first-region-information for the component of which the manufacturing process is determined to be later by the discrimination unit between the first component and the second-component and acquire the second-region-information for the component of which the manufacturing process is determined to be earlier, and a determination unit configured to compare the first-region-information and the second-region-information so as to determine presenc
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: February 16, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Masato Ariyama, Kazuhiro Sakai
  • Publication number: 20130090753
    Abstract: A design-support-apparatus includes a storage unit that stores mounting information on an order of manufacturing processes, first-region-information indicating a region to be secured in mounting of each component on the substrate, second-region-information indicating a region occupied when each component is mounted on the substrate, a discrimination unit configured to determine a before-and-after relationship between manufacturing processes of mounting a first-component and a second-component that are arranged on the substrate, an acquisition unit configured to acquire the first-region-information for the component of which the manufacturing process is determined to be later by the discrimination unit between the first component and the second-component and acquire the second-region-information for the component of which the manufacturing process is determined to be earlier, and a determination unit configured to compare the first-region-information and the second-region-information so as to determine presenc
    Type: Application
    Filed: August 27, 2012
    Publication date: April 11, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Masato ARIYAMA, Kazuhiro SAKAI
  • Publication number: 20120079445
    Abstract: A circuit board designing device has a database that stores an another-component arrangement forbidden range table, a related component information table, and a relative-arranging position table, and a processing unit that executes arrangement of the components, determines the another-component arrangement forbidden range which is set to forbid arrangement of another component in the predetermined range on the basis of the arranging position of the basic component with reference to the another-component arrangement forbidden range table when arrangement of the basic component is instructed, acquires related component information corresponding to the related component to be combined with the basic components with reference to the related component information table, acquires a relative-arranging position of the related component from the relative-arranging position table on the basis of the acquired related component information, and sets the acquired related component in the another-component arrangement forb
    Type: Application
    Filed: August 23, 2011
    Publication date: March 29, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Masato Ariyama, Kazuhiro Sakai
  • Patent number: 7444612
    Abstract: In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a central processing unit) that forms a pin layout matrix (a matrix sheet) by unifying pin layout information of the integrated circuit using a common format and arranging the pin layout information in coordinates. The processor creates an integrated-circuit design library from the pin layout matrix.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: October 28, 2008
    Assignee: Fujitsu Limited
    Inventors: Masato Ariyama, Junko Taira, Kazuyuki Iida, Minoru Yabumoto, Tomohisa Suzuki, Minako Kubota
  • Publication number: 20060059447
    Abstract: In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a central processing unit) that forms a pin layout matrix (a matrix sheet) by unifying pin layout information of the integrated circuit using a common format and arranging the pin layout information in coordinates.
    Type: Application
    Filed: December 21, 2004
    Publication date: March 16, 2006
    Inventors: Masato Ariyama, Junko Taira, Kazuyuki Iida, Minoru Yabumoto, Tomohisa Suzuki, Minako Kubota
  • Patent number: 6117183
    Abstract: Disclosed is an interactive CAD apparatus for logic circuit packaging design, wherein provisions are made to display delay times in real time when a component is being moved, so that error-contributing components and interconnections can be easily identified and the optimum position can be easily determined.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: September 12, 2000
    Assignee: Fujitsu Limited
    Inventors: Mieko Teranishi, Yoshiyuki Iwakura, Masaharu Nishimura, Akira Katsumata, Masato Ariyama
  • Patent number: 5644500
    Abstract: This invention is directed to a method and apparatus to find out an optimum solution in automatic routing or automatic placement with certainty and at a high-speed to improve a routing rate, and to realize automatic routing in a high-density. To these end, a routing approach is selected in a conversational mode while routing efficiency is consulted to compose routing processing procedure so as to generate a routing program. Besides, component placement processing procedures designated according to placement control information are combined to generate the placement program. A straight line between component pins adjacent to each other is defined as a chord, a wave for maze method routing is generated from a start point toward an end point of a routing path and propagated between the chords adjacent to each other.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: July 1, 1997
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Miura, Masato Ariyama, Kazuyuki Iida, Kazufumi Iwahara, Mitsunobu Okano, Hiroyuki Orihara, Akira Katsumata, Toshiyasu Sakata, Masaharu Nishimura, Hirofumi Hamamura, Naoki Murakami, Mitsuru Yasuda, Yasuhiro Yamashita, Ryouji Yamada, Atsushi Yamane