Abstract: The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for transmitting a signal are continuously covered by a conductor layer (12) with insulators (7), (8) and (9) interposed therebetween in a section crossing a direction of extension thereof, and the conductor layer (12) is connected to a semiconductor substrate (1). Moreover, a periphery of a wiring (15) for transmitting a signal is continuously covered by the conductor layer (12) and a conductor layer (19) with insulators (14), (16), (17) and (18) interposed therebetween in a section crossing a direction of extension thereof. The wiring (15) is electrically connected to the semiconductor substrate (1) through a conductive plug (13) filled in a contact hole (24) formed in the conductor layer (12).

Abstract: The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for transmitting a signal are continuously covered by a conductor layer (12) with insulators (7), (8) and (9) interposed therebetween in a section crossing a direction of extension thereof, and the conductor layer (12) is connected to a semiconductor substrate (1). Moreover, a periphery of a wiring (15) for transmitting a signal is continuously covered by the conductor layer (12) and a conductor layer (19) with insulators (14), (16), (17) and (18) interposed therebeween in a section crossing a direction of extension thereof. The wiring (15) is electrically connected to the semiconductor substrate (1) through a conductive plug (13) filled in a contact hole (24) formed in the conductor layer (12).

Abstract: The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for transmitting a signal are continuously covered by a conductor layer (12) with insulators (7), (8) and (9) interposed therebetween in a section crossing a direction of extension thereof, and the conductor layer (12) is connected to a semiconductor substrate (1). Moreover, a periphery of a wiring (15) for transmitting a signal is continuously covered by the conductor layer (12) and a conductor layer (19) with insulators (14), (16), (17) and (18) interposed therebeween in a section crossing a direction of extension thereof. The wiring (15) is electrically connected to the semiconductor substrate (1) through a conductive plug (13) filled in a contact hole (24) formed in the conductor layer (12).

Abstract: A semiconductor device having a self-aligned contact structure. To determine the position of a contact plug in a self-aligned manner, silicon nitride films are provided around a gate electrode and a bitline, respectively. Between the gate electrode and bitline, and the silicon nitride films are provided low dielectric constant insulation films having a dielectric constant lower than that of the silicon nitride films. Further, the low dielectric constant insulation films are provided in contact with the gate electrode and bitline. The presence of the low dielectric constant insulation films suppresses the increase in parasitic capacitance resulting from the presence of the silicon nitride films between the gate electrode and bitline, and the contact plug.

Abstract: A semiconductor device having a self-aligned contact structure is provided. To determine the position of a contact plug (12) in a self-aligned manner, silicon nitride films (5, 10) are provided around a gate electrode (3) and a bitline (8), respectively. Between the gate electrode (3) and bitline (8), and the silicon nitride films (5, 10) are provided low dielectric constant insulation films (4a, 4b, 7, 9a, 9b) having a dielectric constant lower than that of the silicon nitride films, the low dielectric constant insulation films being provided in contact with the gate electrode (3) and bitline (8). The presence of the low dielectric constant insulation films (4a, 4b, 7, 9a, 9b) suppresses the increase in parasitic capacitance resulting from the presence of the silicon nitride films (5, 10) between the gate electrode (3) and bitline (8), and the contact plug (12).

Abstract: A semiconductor device capable of controlling an electric potential of an electric conductor to reduce both a leakage caused by a punch-through and a junction leakage in a trench isolating structure having the electric conductor in a trench portion. In a trench isolating structure, an insulating film is disposed on an inner surface of a trench provided in a silicon substrate and doped polysilicon doped with phosphorus in a concentration of approximately 1×1020/cm3, for example, is buried as an electric conductor in a lower side of a trench space defined by the insulating film. In addition, a silicon oxide is buried as an insulator in an upper side of the trench space. For the silicon oxide to be used, a TEOS oxide film, a HDP oxide film or a SiOF film having a small dielectric constant may be buried.

Abstract: The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for transmitting a signal are continuously covered by a conductor layer (12) with insulators (7), (8) and (9) interposed therebetween in a section crossing a direction of extension thereof, and the conductor layer (12) is connected to a semiconductor substrate (1). Moreover, a periphery of a wiring (15) for transmitting a signal is continuously covered by the conductor layer (12) and a conductor layer (19) with insulators (14), (16), (17) and (18) interposed therebeween in a section crossing a direction of extension thereof. The wiring (15) is electrically connected to the semiconductor substrate (1) through a conductive plug (13) filled in a contact hole (24) formed in the conductor layer (12).

Abstract: A technique of correcting a mask pattern without alleviating the design rule or measuring all contact hole diameters. Undulations are inspected in a region for forming contact holes (step S3). On the basis of the surface shape (undulations) determined at step S3, the contact hole diameter is predicted in the case of use of the mask hole diameter fabricated at step S1 (step S4). On the basis of the result of prediction, the mask pattern M is corrected to mask patter M′ according to the mask hole diameter (step S5).

Abstract: A method of manufacturing a semiconductor device wherein the device is manufactured according to extracted process parameters. The process parameters are extracted as a set of optimum process parameters which satisfy an intended specification using process functions. The process functions describe a characteristic of the semiconductor device, and are determined using experimental values and/or simulated values. The process parameters may then be transmitted online to a factory.

Abstract: An area to which volume ratio "1" as allotted in an analysis area is divided into first and second types of cells. A third cell is placed next to and above the first cell, and volume ratio "0" is allotted to the third cell. With respect to the direction in which the third and first cells are placed next to each other, both cells are adapted to have the same width. As a result, by interpolation of the volume ratio, the position at which volume ratio assumes 0.5 is positioned at the boundary between cells.

Abstract: Improved setup of process parameters for manufacturing of a semiconductor device is disclosed. Using parameters which are necessary for attaining a threshold voltage of a semiconductor device, process simulation is performed to thereby compute the threshold voltage. Whether the computed threshold voltage has a predetermined value is then judged. The parameters are updated until the predetermined value is reached. The simulation involves partitioning the semiconductor device into fine discrete cells. A boundary region is defined which delineates neighboring cells. Since a range of the boundary region is considered in the simulation, prediction of impurity concentration is accurate.

Abstract: A semiconductor device for switching comprises a semiconductor substrate (10), three conductive regions (14, 16, 20) for providing a path for electrons to or from desired locations of the semiconductor substrate (10) formed at locations spaced apart on the surface of the semiconductor substrate (10, 28), a device (22, 24) for causing a current between the first and second conductive regions (14, 16), and a device (18) for forming electric field for diverting the caused current to the third conductive region (20). Since the current flowing to the first and second conductive regions (14, 16) is diverted to the third conductive region (20), switching operation between the first and second conductive regions (14, 16) is implemented.

Abstract: A method of predicting the topography of a semiconductor workpiece after a plurality of manufacturing processes, such as etching and film deposition, are carried out on the workpiece includes establishing a desired topography for a semiconductor workpiece after sequential performance of a plurality of processes, such as etching, are carried out on the workpiece; specifying conditions, such as temperature and etchant concentration, for each process; establishing a plurality of points in a grid in a space including the workpiece; identifying the materials comprising the workpiece and the concentration of virtual particles representing the topography of the workpiece before a first process; using the modified diffusion model equation to predict the material and concentration of virtual particles after the completion of the first process in the sequence of processes; recording the material and virtual particle concentration at the completion of the first process as a decimal number including an integer part repre

Abstract: A shape simulation method includes dividing an analysis volume into a plurality of cells, defining an initial volume ratio of the volume of a substance in a cell to the volume of the cell for each cell, computing the in flow and the out flow of the substance in each cell every time a very small time period elapses, computing a volume ratio for each cell from the initial volume and the in flow and out flow of the substance every time a very small time period elapses, and simulating the surface shape of the substance with the cells having a volume ratio of a predetermined value.

Abstract: A topography simulation method for simulating a surface topography of a material object material while a surface of material object is being processed, as by etching or a deposition, includes the steps of dividing a region to be analyzed, in a surface including the advancing direction of processing, into a plurality of regions in a grid in accordance with the surface topography of the material object by approximating the movement of the processed surface of the material object as the movement of an equi-concentration surface determined by the diffusion of particles, establishing diffusion coefficients for the respective regions on the basis of the surface processing velocity, calculating equi-concentration surfaces by the Diffusion equation, and assembling the obtained equi-concentration surfaces to produce a three-dimensional surface topography.

Abstract: A topography simulation method enables estimation of the three-dimensional shape of a surface of a workpiece where material removal by a predetermined process takes place. This simulation method includes the steps of dividing a region of the workpiece to be removed into a plurality of partial regions; setting a diffusion coefficient for each partial region with a diffusion component contributing to material removal, and calculating a contour surface of the concentration of the diffusion component by a process which employs modified diffusion equations. The contour surface obtained the surface after material removal.

Abstract: A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).