Abstract: A transmission apparatus includes a first circuit, a second circuit, and a connector that couples the first circuit and the second circuit to each other, the first circuit includes a signal generation circuit that outputs an alternate current signal of a predetermined power at a frequency from a carrier frequency to three times the carrier frequency, and one of the first circuit and the second circuit includes a determination circuit that evaluates a fit state at the connector by determining whether the first circuit and the second circuit are fitted to each other via the connector based on the predetermined power and a power of the alternate current signal received by the determination circuit via the connector.

Abstract: The communication apparatus includes a logical device, a wiring line, and a changing unit; the logical device is a programmable device; the wiring line supplies a voltage to the logical device; and the changing unit changes a frequency characteristic of the wiring line based on an operating characteristic obtained by monitoring of the operating characteristic of the logical device for operating by receiving supply of the voltage. According to this, occurrence of voltage drop can be suppressed even if a circuit configured in a programmable logical device is changed.

Abstract: A communication device includes a reception buffer configured to receive a pulse signal cyclically transmitted from a transmission source device via a transmission line; a branch circuit configured to generate a branch pulse signal by branching the pulse signal; a delay circuit configured to add a predetermined delay time to the generated branch pulse signal; and a transmission buffer configured to transmit the branch pulse signal to which the predetermined delay time was added to the transmission source device via the transmission line.

Abstract: A communication device includes a reception buffer configured to receive a pulse signal cyclically transmitted from a transmission source device via a transmission line; a branch circuit configured to generate a branch pulse signal by branching the pulse signal; a delay circuit configured to add a predetermined delay time to the generated branch pulse signal; and a transmission buffer configured to transmit the branch pulse signal to which the predetermined delay time was added to the transmission source device via the transmission line.

Abstract: A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.

Abstract: A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.

Abstract: An abnormality in operation is detected by meticulously monitoring the operation of a monitored device that comprises a state machine. The state number, indicating the state the monitored device is currently in, is output from the device. The upper and lower limit values of current consumption is set for each state number. A monitoring circuit, using the upper and lower limit values for the present state number, judges the value of current consumption detected by a current detection circuit and detects whether there is abnormality in operation.

Abstract: A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.

Abstract: A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.

Abstract: An abnormality in operation is detected by meticulously monitoring the operation of a monitored device that comprises a state machine. The state number, indicating the state the monitored device is currently in, is output from the device. The upper and lower limit values of current consumption is set for each state number. A monitoring circuit, using the upper and lower limit values for the present state number, judges the value of current consumption detected by a current detection circuit and detects whether there is abnormality in operation.

Abstract: If wavelengths ?a and ?b are dropped in NE (Network Equipment) 2 and a wavelength ?c is made Through, and all of wavelengths are made Through in NE3 in a certain time period, a route from NE1 to NE2, a route from NE2 to NE4, and a route from NE1 to NE4 are established. If a user who uses the wavelength ?a from NE1 to NE2, and a user who uses the wavelength ?b from NE2 to NE4 do not use the routes in another time period, and if another user desires to use a route from NE1 to NE3 and a route from NE3 to NE4, the routes are reestablished in a way such that the wavelength ?a is converted into the wavelength ?b and made Through in NE2, and the wavelength ?b is dropped and added in NE3.

Abstract: A transmission device and an integrated circuit improved in quality and reliability of digital transmission control. A memory stores an input signal, write address generating means generates a write address for writing in the memory, and read address generating means generates a read address for reading from the memory. Phase state monitoring means monitors a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided. When the coincident phase state or the unstable phase state is detected, reset signal output means outputs a reset signal to the write and read address generating means such that the phase relation between the write and read addresses is brought to an optimum phase relation.