Patents by Inventor Masato Hori

Masato Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10628356
    Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kenichi Miyama, Masato Hori
  • Publication number: 20190155776
    Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 23, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Kenichi Miyama, MASATO HORI
  • Patent number: 9678913
    Abstract: A control apparatus that controls one or more first communication apparatuses and one or more second communication apparatuses configured to identify a logic level of a signal, the control apparatus includes a memory; and a processor coupled to the memory and configured to: acquire, from one of the one or more second communication apparatuses, a length of an undefined time period during which a level of the signal is undefined; determine, based on the length of the undefined time period, a length of a protection time period indicating a time period during which a logic level of the signal received by the second communication apparatus is maintained at a same level; and determine, based on the length of the protection time period, a rate of a signal transmitted to one of the one or more second communication apparatuses by one of the one or more first communication apparatuses.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 13, 2017
    Assignee: Fujitsu Limited
    Inventors: Kenichi Miyama, Masato Hori
  • Patent number: 9436211
    Abstract: A clock conversion apparatus comprising, an elastic store memory in which data are written in synchronization with a first clock and from which data are read out in synchronization with a second clock, a phase comparator for detecting phase difference between a third clock obtained by imparting a first variable phase shift to a divided clock of the first clock and a fourth clock obtained by imparting a second variable phase shift to a divided clock of the second clock, and an oscillator for generating a clock having frequency in accordance with the phase difference as the second clock.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 6, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Makoto Shimizu, Masato Hori
  • Publication number: 20160150428
    Abstract: A control apparatus that controls one or more first communication apparatuses and one or more second communication apparatuses configured to identify a logic level of a signal, the control apparatus includes a memory; and a processor coupled to the memory and configured to: acquire, from one of the one or more second communication apparatuses, a length of an undefined time period during which a level of the signal is undefined; determine, based on the length of the undefined time period, a length of a protection time period indicating a time period during which a logic level of the signal received by the second communication apparatus is maintained at a same level; and determine, based on the length of the protection time period, a rate of a signal transmitted to one of the one or more second communication apparatuses by one of the one or more first communication apparatuses.
    Type: Application
    Filed: October 19, 2015
    Publication date: May 26, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Kenichi Miyama, MASATO HORI
  • Patent number: 8855191
    Abstract: High-quality video encoding may be implemented using a single-chip multiprocessor system. Video encoding may be parallelized to take advantage of multiple processing elements available on a single-chip multiprocessor system. Task level parallelism may comprise parallelizing encoding tasks, such as motion estimation, compensation, transformation, quantization, deblocking filtering, and the like across multiple processing elements. Data level parallelism may comprise segmenting video frame data into macroblock partitions and slabs adapted to provide data independence between parallel processing elements. Data communications and synchronization features of the single-chip system may be leveraged to provide for data sharing and synchronism between processing elements.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: October 7, 2014
    Assignee: Broadcast International, Inc.
    Inventors: J. Dean Brederson, Greg Gillis, Sean Heffernan, Daichi Furusaka, Keishi Chikamura, Masato Hori, Di Wu, Lim Boon Shyang
  • Publication number: 20130232371
    Abstract: A clock conversion apparatus comprising, an elastic store memory in which data are written in synchronization with a first clock and from which data are read out in synchronization with a second clock, a phase comparator for detecting phase difference between a third clock obtained by imparting a first variable phase shift to a divided clock of the first clock and a fourth clock obtained by imparting a second variable phase shift to a divided clock of the second clock, and an oscillator for generating a clock having frequency in accordance with the phase difference as the second clock.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 5, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Makoto SHIMIZU, Masato HORI
  • Patent number: 8244258
    Abstract: A critical threshold value of the number of connections of VoIP communication by a wireless LAN is set to an access point apparatus. The access point apparatus records identification information of terminals each of which has transmitted a request for connection of VoIP communication. After the number of terminals whose identification information have been recorded reaches the critical threshold value, the access point apparatus transmits a packet indicating release an association to a terminal whose identification information is newly recorded.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: August 14, 2012
    Assignee: NEC Infrontia Corporation
    Inventor: Masato Hori
  • Publication number: 20100246665
    Abstract: High-quality video encoding may be implemented using a single-chip multiprocessor system. Video encoding may be parallelized to take advantage of multiple processing elements available on a single-chip multiprocessor system. Task level parallelism may comprise parallelizing encoding tasks, such as motion estimation, compensation, transformation, quantization, deblocking filtering, and the like across multiple processing elements. Data level parallelism may comprise segmenting video frame data into macroblock partitions and slabs adapted to provide data independence between parallel processing elements. Data communications and synchronization features of the single-chip system may be leveraged to provide for data sharing and synchronism between processing elements.
    Type: Application
    Filed: November 24, 2009
    Publication date: September 30, 2010
    Applicant: BROADCAST INTERNATIONAL
    Inventors: J. Dean Brederson, Greg Gillis, Sean Heffernan, Daichi Furusaka, Keishi Chikamura, Masato Hori, Di Wu, Lim Boon Shyang
  • Patent number: 7801134
    Abstract: A VoIP system has a VoIP server and plural clients. The client transmits paging data as multicast packets addressed at a specific multicast address, to other clients. In response to a request from the client, the VoIP server transmits multicast packets of MOH data to the other clients. At this time, whether the other clients can receive multicast packets is determined. To the clients that are determined to be capable of receiving multicast packets, transmission data is sent in the form of multicast packets. To the client which belongs to a router and is determined to be incapable of receiving multicast packets, the transmission data is sent as unicast packets. It is thus possible for the VoIP system to support paging and MOH in the form of multicast packets, with respect to clients incapable of receiving multicast.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: September 21, 2010
    Assignee: NEC Infrontia Corporation
    Inventors: Masato Hori, Yoshikazu Kobayashi
  • Patent number: 7715383
    Abstract: According to an embodiment, previous data group input time is subtracted from current data group input time in order to obtain a difference time each time a data group is input. The difference time is subtracted from a packet transmission interval in order to obtain an interval difference. The interval difference is added to a total difference time. If the total difference time is not greater than the first predetermined value, then the input data group is transmitted as a packet. Otherwise, the input data group is discarded and the total difference time is initialized to a value obtained by subtracting the packet transmission interval from the first predetermined value, if the total difference time is greater than the first predetermined value.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: May 11, 2010
    Assignee: NEC Infrontia Corporation
    Inventor: Masato Hori
  • Patent number: 7454919
    Abstract: Defrosting operation is possible by causing refrigerant discharged from a compressor to flow to an outdoor heat exchanger, and returning the refrigerant passed through the outdoor heat exchanger to the compressor through a water-heat exchanger, while operating a pump. Quick defrosting operation is possible by causing refrigerant discharged from a compressor to flow to an outdoor heat exchanger, and returning the refrigerant passed through the outdoor heat exchanger directly to the compressor, while stopping a pump. The temperature of water that has flowed into a water-heat exchanger is detected. According to the detected temperature, the defrosting operation using hot water and quick defrosting operation are selectively executed.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 25, 2008
    Assignee: Toshiba Carrier Corporation
    Inventors: Seiji Ookoshi, Tomoaki Tanabe, Masaaki Sato, Masato Hori, Yoshiteru Yamazaki
  • Patent number: 7420925
    Abstract: A first wireless LAN base station is in an active state. A second wireless LAN base station is in a power off state or a power save mode. The first wireless LAN base station and the second wireless LAN base station are disposed in the same support area. When a fault occurs in the first wireless LAN base station and a communication state of the wireless LAN deteriorates, the first wireless LAN base station detects the fault and places the second wireless LAN base station in the active state. When the first wireless LAN base station confirms that the second wireless LAN base station has been placed in the active state, the first wireless LAN base station sends setting thereof to the second wireless LAN base station. When the first wireless LAN base station confirms that the setting of the second wireless LAN base station is the same as the setting of the first wireless LAN base station, the first wireless LAN base station enters the power off state or the power save mode.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: September 2, 2008
    Assignee: NEC Infrontia Corporation
    Inventors: Masato Hori, Yoshikazu Kobayashi
  • Publication number: 20080092568
    Abstract: Defrosting operation is possible by causing refrigerant discharged from a compressor to flow to an outdoor heat exchanger, and returning the refrigerant passed through the outdoor heat exchanger to the compressor through a water-heat exchanger, while operating a pump. Quick defrosting operation is possible by causing refrigerant discharged from a compressor to flow to an outdoor heat exchanger, and returning the refrigerant passed through the outdoor heat exchanger directly to the compressor, while stopping a pump. The temperature of water that has flowed into a water-heat exchanger is detected. According to the detected temperature, the defrosting operation using hot water and quick defrosting operation are selectively executed.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 24, 2008
    Applicant: TOSHIBA CARRIER CORPORATION
    Inventors: SEIJI OOKOSHI, Tomoaki Tanabe, Masaaki Sato, Masato Hori, Yoshiteru Yamazaki
  • Publication number: 20070297368
    Abstract: A critical threshold value of the number of connections of VoIP communication by a wireless LAN is set to an access point apparatus. The access point apparatus records identification information of terminals each of which has transmitted a request for connection of VoIP communication. After the number of terminals whose identification information have been recorded reaches the critical threshold value, the access point apparatus transmits a packet indicating release an association to a terminal whose identification information is newly recorded.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 27, 2007
    Applicant: NEC INFRONTIA CORPORATION
    Inventor: Masato HORI
  • Publication number: 20070201507
    Abstract: A frame transmitting method and device insert a channel identifier into predetermined free bytes of parallel channel signals whose phases are different from each other without a phase adjustment, and convert the parallel channel signals into a serial signal to transmit a frame. A frame receiving method and device convert a serial signal whose phase is not adjusted on the transmission side into parallel channel signals, detect a frame pattern from a single channel signal within the parallel channel signals to detect a channel identifier inserted into a predetermined free byte of the single channel signal, and further rearrange channels between all of the parallel channel signals without a phase adjustment, based on the channel identifier.
    Type: Application
    Filed: August 11, 2006
    Publication date: August 30, 2007
    Inventors: Yukio Yamazaki, Masato Hori, Waki Iwata
  • Patent number: 7221667
    Abstract: In a wireless LAN communication system, a communication mode is automatically switched between an infrastructure mode and an ad-hoc mode. Communication between two stations is started in the infrastructure mode. Packets transmitted in an infrastructure network are monitors to detect a packet transmitted to an access point and addressed, as a final destination, to one's own station or a destination station. If such a packet is detected, it is determined that a transmitting or source station is in a state that allows an ad-hoc communication. A channel searcher of the access point searches for available channels of an ad-hoc network. A switching controller selects one of the available channels and transmits information indicating the selected channel to the source and destination stations. In response to receiving the information indicating the selected channel, the source and destination stations starts direct communication using the selected channel of the ad-hoc network.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: May 22, 2007
    Assignee: NEC Infrontia Corporation
    Inventors: Masato Hori, Yoshikazu Kobayashi
  • Publication number: 20060023714
    Abstract: According to an embodiment, previous data group input time is subtracted from current data group input time in order to obtain a difference time each time a data group is input. The difference time is subtracted from a packet transmission interval in order to obtain an interval difference. The interval difference is added to a total difference time. If the total difference time is not greater than the first predetermined value, then the input data group is transmitted as a packet. Otherwise, the input data group is discarded and the total difference time is initialized to a value obtained by subtracting the packet transmission interval from the first predetermined value, if the total difference time is greater than the first predetermined value.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Inventor: Masato Hori
  • Patent number: 6845125
    Abstract: An xDSL transceiver comprising a transmission unit for transmitting a DMT-modulated signal through a subscriber line as a transmission path and a receiving unit for receiving the DMT-modulated signal from the subscriber line. The xDSL transceiver further comprises an echo signal suppression unit for suppressing the echo signal from the transmission unit to the receiving unit by matching the phase between the frame of the transmission signal and the frame of the receiving signal.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: January 18, 2005
    Assignee: Fujitsu Limited
    Inventors: Takashi Sasaki, Masato Hori, Kumiko Maruo, Akira Oshima, Noriyasu Suzuki, Yoichi Ueda
  • Patent number: 6845406
    Abstract: Prior to the initialization, CPU of information processing equipment makes a decision about whether a communication line has been connected to a connector or not. When the two are connected, the CPU does not carry out the initialization and shifts xDSL modem to lower power consumption mode. The connection is checked as follows. A test signal is transmitted through the xDSL modem. This signal is reflected by the connector and reflection is received by hybrid circuit. When the energy of this echo is large it means that the communication line it not connected to the connector, when the energy is small it means that the two are connected.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: January 18, 2005
    Assignee: Fujitsu Limited
    Inventors: Masato Hori, Akira Oshima, Kentaro Fukushima