Abstract: A quick charging device includes a battery capable of quickly charging a battery for power, the battery for power being a load, a high-capacity battery having a higher electrical capacitance than the battery, and a controller configured to, when the battery for power is charged, connect the battery and the high-capacity battery in series to add power of the high-capacity battery to power of the battery, and supply the battery for power with the power obtained through the addition.

Abstract: A rapid charger includes a storage battery for equipment, a DC power supply unit which converts AC power of an AC power supply into DC power, and a controller which controls the DC power supply unit such that the DC power supply unit generates DC power to charge the storage battery for equipment from the AC power of the AC power supply and allows the DC power to be supplied from the DC power supply unit to the storage battery for equipment during charging of the storage battery for equipment, wherein, when a storage battery for driving power as a load is connected, the controller allows the DC power supply unit and the storage battery for equipment to form a series circuit, controls the DC power supply unit such that the DC power supply unit generates a predetermined DC power from the AC power of the AC power supply, adds the predetermined DC power to the DC power of the storage battery for equipment to generate DC power to charge the storage battery for driving power, and allows the DC power to be supplied t

Abstract: A quick charging device for charging a battery includes a battery with a high power density (a high-power-density battery) and a battery with a high energy density (a high-energy-density battery).

Abstract: A dual-power type integrated circuit includes a ground terminal GND, a power source terminal VCC associated with the terminal GND to receive 3.3 V, a power source terminal VCCQ associated with the terminal GND to receive 2.5 V, an N-type semiconductor substrate 80 connected to the terminal VCC, a P-type well region 90 formed in the N-type semiconductor substrate and connected to the terminal GND, a logic processing section 50 which includes CMOS transistors 52, 54 formed in the N-type semiconductor substrate 80 and the P-type well region 90 and connected to operate at 3.3 V, and generates a logic signal with voltage amplitude of 3.3 V, and a voltage amplitude converting section 60 which includes CMOS transistors 62 and 64 formed in the N-type semiconductor substrate 80 and the P-type well region 90 and connected to operate at 2.5 V, and converts the logic signal from the logic processing section 50 to have voltage amplitude of 2.5 V.