Patents by Inventor Masato Irikura

Masato Irikura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8723219
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra10 nm and Ra5 ?m at edges of wafers.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: May 13, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Publication number: 20130292696
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra10 nm and Ra5 ?m at edges of wafers.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 7, 2013
    Inventors: MASAHIRO NAKAYAMA, MASATO IRIKURA
  • Patent number: 8482032
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: July 9, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Patent number: 8283694
    Abstract: A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013, wherein a plane orientation of the surface is any of a (0001) plane, a (11-20) plane, a (10-12) plane, a (10-10) plane, a (20-21) plane, a (10-11) plane, a (11-21) plane, a (11-22) plane, and a (11-24) plane of a wurtzite structure.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 9, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20120094473
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (1) is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface (3) is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface (3) is not more than 3×1013, and a haze level of the surface (3) is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and a haze level of the surface (3) is not more than 5 ppm.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 19, 2012
    Inventors: Keiji ISHIBASHI, Akihiro HACHIGO, Masato IRIKURA, Seiji NAKAHATA
  • Patent number: 8101968
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface is not more than 3×1013, and a haze level of the surface is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and a haze level of the surface is not more than 5 ppm.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110297959
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Application
    Filed: August 17, 2011
    Publication date: December 8, 2011
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro NAKAYAMA, Masato Irikura
  • Patent number: 8022438
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: September 20, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura
  • Publication number: 20110146565
    Abstract: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Inventors: Keiji ISHIBASHI, Naoki MATSUMOTO, Masato IRIKURA
  • Publication number: 20110133209
    Abstract: A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013, wherein a plane orientation of the surface is any of a (0001) plane, a (11-20) plane, a (10-12) plane, a (10-10) plane, a (20-21) plane, a (10-11) plane, a (11-21) plane, a (11-22) plane, and a (11-24) plane of a wurtzite structure.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji ISHIBASHI, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Publication number: 20110133207
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate (1) is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface (3) is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface (3) is not more than 3×1013, and a haze level of the surface (3) is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface (3) is not more than 2×1014, and a haze level of the surface (3) is not more than 5 ppm.
    Type: Application
    Filed: January 28, 2011
    Publication date: June 9, 2011
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Patent number: 7919343
    Abstract: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: April 5, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Naoki Matsumoto, Masato Irikura
  • Patent number: 7901960
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface is not more than 3×1013, and a haze level of the surface is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid, material per square centimeter of a surface is not more than 2×1014, and a haze level of the surface is not more than 5 ppm.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Patent number: 7851381
    Abstract: A surface treatment method for a nitride crystal is a surface treatment method of chemically and mechanically polishing a surface of the nitride crystal. Oxide abrasive grains are used. The abrasive grains have a standard free energy of formation of at least ?850 kJ/mol as a converted value per 1 mole of oxygen molecules and have a Mohs hardness of at least 4. The surface treatment method efficiently provides, for efficiently obtaining a nitride crystal substrate that can be used for a semiconductor device, the nitride crystal having the smooth and high-quality surface formed thereon.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: December 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Takayuki Nishiura, Masato Irikura, Seiji Nakahata
  • Publication number: 20100187540
    Abstract: A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate is one of the following: a group III nitride substrate, wherein the number of atoms of an acid material per square centimeter of a surface is not more than 2×1014, and the number of silicon atoms per square centimeter of the surface is not more than 3×1013; a group III nitride substrate, wherein the number of silicon atoms per square centimeter of a surface is not more than 3×1013, and a haze level of the surface is not more than 5 ppm; and a group III nitride substrate, wherein the number of atoms of an acid, material per square centimeter of a surface is not more than 2×1014, and a haze level of the surface is not more than 5 ppm.
    Type: Application
    Filed: October 9, 2007
    Publication date: July 29, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES , LTD.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Masato Irikura, Seiji Nakahata
  • Patent number: 7662239
    Abstract: Quality of one-surface planar processed group 3 nitride wafers depends upon a direction of pasting of wafers on a polishing plate. Low surface roughness and high yield are obtained by pasting a plurality of group 3 nitride as-grown wafers on a polishing plate with OFs or notches facing forward (f), backward (b) or inward (u) with thermoplastic wax having a thickness of 10 ?m or less, grinding the as-grown wafers, lapping the ground wafers, polishing the lapped wafers into mirror wafers with a bevel of a horizontal width of 200 ?m or less and a vertical depth of 100 ?m or less.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: February 16, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Masato Irikura, Seiji Nakahata
  • Publication number: 20100013058
    Abstract: Affords semiconductor wafers that achieve uniformization of semiconductor films. In a semiconductor wafer (1), between one and twenty pinholes (3) are formed per wafer for two-inch diameter semiconductor wafers (1). An effect whereby the warp in the semiconductor wafer (1) following semiconductor film formation is reduced, and dimensional variation following photolithographic exposure is reduced can thereby be obtained. This is presumed to be because dislocations in the semiconductor wafer (1) front side are extinguished by the presence of the pinholes (3). Accordingly, this can serve to make the quality of the semiconductor films consistent, make the performance of semiconductor devices consistent, and prevent fracture of the semiconductor wafer (1).
    Type: Application
    Filed: October 3, 2008
    Publication date: January 21, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kaoru Shibata, Shinji Okabayashi, Yasuhiro Honzu, Masato Irikura, Fumitake Nakanishi
  • Publication number: 20090273060
    Abstract: A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 5, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji ISHIBASHI, Naoki Matsumoto, Masato Irikura
  • Publication number: 20090218659
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Application
    Filed: May 6, 2009
    Publication date: September 3, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masahiro NAKAYAMA, Masato Irikura
  • Patent number: 7550780
    Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: June 23, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masahiro Nakayama, Masato Irikura