Abstract: An antenna mirror surface measuring/adjusting apparatus has a plane mirror larger than an aperture surface of said principal reflection mirror and set in parallel with the aperture surface, an actuator for driving a group of mirror surface panels of the principal reflection mirror, and a receiving electric field arithmetic processor for measuring, each time the actuator shifts a position of the mirror surface panel from an initial state of the mirror surface panel of the principal reflection mirror, radio wave signals of radio waves radiated by a transmitter/receiver and reflected back from the plane mirror, obtaining an aperture surface phase distribution in an initial state of the principal reflection mirror by executing an arithmetic process on these measured signals, then gaining configurations of the mirror surface on the basis of the aperture surface phase distribution, and adjusting the mirror surface by the actuator in accordance with the obtained mirror surface configurations.

Abstract: A master slice type integrated circuit in which various circuits may be formed by varying the routing of interconnections, comprises a plurality of input/output cells being arranged in a peripheral region on a semiconductor chip; a plurality of basic cell columns each comprising a plurality of basic cells arranged in a predetermined direction, each basic cell constituting transistors; an interconnection region formed on the chip, for accommodating a data bus; and a plurality of latch cells being arranged in the basic cell columns, for keeping a potential of a data bus laid on the interconnection region to prevent the data bus from being changed into a floating state, each latch cell comprising transistors, each of which has a driving capability smaller than that of each transistor of the basic cell.

Abstract: A gate array is disclosed having a plurality of basic cells each comprising a transistor whose gm is as low as one fifth to one twentieth that of the transistors in a conventional gate array. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell having the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array. The transistor of low gm reduces the number of basic cells necessary for forming a delay circuit, and elminates the need for an external resistance component which was formerly required when a pull-up or pull-down circuit or a monostable multivibrator was formed in the gate array.

Abstract: An integrated circuit having a frequency-dividing circuit which can be tested at high speeds, in which the frequency-dividing circuit is separated into a first stage frequency-dividing circuit and a second stage frequency-dividing circuit, an output buffer circuit and a test signal input circuit are connected to an alarm terminal parallelly, and test signals applied to the alarm terminal are supplied to the second stage frequency-dividing circuit via the test signal input circuit and a switching circuit.