Abstract: An organic EL device includes an emitting region and a first anode side organic layer. The first anode side organic layer contains a first material. The emitting region includes a first emitting layer containing first and second host materials and a second emitting layer containing a third host material.

Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.

Abstract: A trench gate power MOSFET (1) of the present invention includes an n-type epitaxial layer (12), gates (18) and MOSFET cells. The gate (18) is disposed in a trench (14) formed in a surface of the n-type epitaxial layer (12). The MOSFET cell is formed on the surface of the n-type epitaxial layer (12) so as to be in contact with side surfaces of the trench (14). The trench gate power MOSFET (1) further includes a p-type isolation region (26) formed on the surface of the n-type epitaxial layer (12) and disposed between the MOSFET cells adjacent to each other in the extending direction of the trench (14) out of the MOSFET cells, and has a pn-junction diode formed between the p-type isolation region (26) and the n-type epitaxial layer (12). According to the trench gate power MOSFET (1) of the present invention, the increase of a diode leakage current with the elevation of temperature can be suppressed.

Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.

Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.

Abstract: An example semiconductor device is capable of preventing a buried diffusion region formed near the bottom surface of a source trench from diffusing to the extent that it contacts a gate trench in the vicinity of that buried diffusion region even if the accuracy of the photographic step of trench formation is not so high. A side wall is formed on the circumferential side of the source trench and then impurities are injected to the bottom surface of the source trench. When the impurities are heated and diffused, the buried P+-type diffusion region is formed with a width almost identical to the width of the opening of the source trench or smaller than the width of the opening of the source trench. Thus, even when irregularities are generated in the manufacturing step and the buried diffusion region becomes larger than is necessary, it is possible to prevent contact of the buried diffusion region with the gate trench.

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the withstand voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.

Abstract: A semiconductor device capable of preventing a buried diffusion region formed near the bottom surface of a source trench from diffusing to the extent that it contacts a gate trench in the vicinity of that buried diffusion region even when the accuracy of the photographic step of trench formation is not so high. A side wall is formed on the circumferential side of the source trench (21) and then impurities are injected to the bottom surface of the source trench (21). When the impurities are heated and diffused, the buried P+-type diffusion region (14) is formed with a width almost identical to the width of the opening of the source trench (21) or smaller than the width (B) of the opening of the source trench (21). Thus, even when irregularities are generated in the manufacturing step and the buried diffusion region (14) becomes larger than is necessary, it is possible to prevent contact of the buried diffusion region (14) with the gate trench (20).

Abstract: The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the withstand voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed with the bottom of the trench at a comparatively shallow position in an N-epitaxial layer 18. The thickness of a bottom surface part 16 of a gate electrode film 11 is formed so as to be thicker than other parts of the gate electrode film 11. Also, when a P type body layer 19 is formed, an interface between the P type body layer 19 and an N-epitaxial layer 18 is located at a deeper position than a bottom end of the gate electrode film 11.