Abstract: A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.

Abstract: A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.

Abstract: Power supply voltage step-down circuitry comprises a control unit for enabling either a first voltage step-down unit or a second voltage step-down unit according to a control signal applied thereto, a voltage checking unit for checking whether or not the value of a voltage generated by a power supply is equal to or greater than a predetermined value, and for furnishing a checking result signal at a predetermined level when the value of the voltage generated by the power supply is equal to or greater than a predetermined value, and a switching unit for connecting either the power supply or an output of the first step-down unit with a receiver, such as a ROM, according to whether or not the checking result signal from the voltage checking unit is at the predetermined level.

Abstract: A voltage drop circuit for generating an active voltage to be supplied to a ROM by dropping a supply voltage. The voltage drop circuit inhibits an access of a CPU to the ROM for a predetermined time period immediately after the ROM shifts from a standby mode to an active mode. This makes it possible to solve a problem of a conventional voltage drop circuit in that it is not unlikely that the CPU cannot read data correctly from the ROM for a moment immediately after the ROM shifts from the standby mode to the active mode because of fluctuations of the active voltage in that moment.

Abstract: The present invention includes a redundant circuit for addressing redundant memory cells. The redundant circuit solves a problem of a conventional redundant circuit caused by injection of electrons into and leakage of electrons from a floating gate of a non-volatile memory cells provided for respective bits of the addressing circuit of the redundant circuit. The redundant circuit has a timer that counts an elapsed time from power-on of the redundant circuit. The timer produces a timing signal when a fixed duration time period has elapsed. A breaker breaks the application of a supply voltage to the gate of a non-volatile memory cell in response to the timing signal.

Abstract: A microcomputer for emulation which has been conventionally unusable when built-in RAM capacities are different, because an access to an internal function circuit is different in bus control, wait condition and the like from the access to an external memory area, and despite the above fact, which now becomes usable by including a built-in RAM 17, a higher address decoder (virtual RAM address decoder) for generating a virtual RAM address space corresponding to a plurality of virtual RAM capacities within a range in which installed capacity of the built-in RAM 17 is made a maximum value, and a RAM capacity selection flag 36 for specifying any one of a plurality of virtual RAM address spaces which can be generated by the higher address decoder 22.

Abstract: A timer apparatus which is provided with a control circuit 80, annexed to each of timers 1-1, 1-2 and 1-3 generating a control signal making the register 3 write data outputted from a CPU 50 when both a write signal 5 generated by the CPU 50 for writing data into the registers 3, and a timer single write signal 11 for specifying any of the timers, are generated, and furthermore is provided with a selection circuit 70 making each control circuit 80 generate a control signal when both the write signal 5 and a timer grouping signal 14 generated for specifying each of the plurality of timers 1-1, 1-2 and 1-3, are generated. When it is necessary that identical data be held in the respective registers 3 of the plurality of timers 1-1, 1-2 and 1-3, the identical data can be written into each of the registers 3 at the same time.