Patents by Inventor Masato Miyamoto

Masato Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200284013
    Abstract: A flush toilet includes: a bowl; at least one water discharge port to discharge water into the bowl; a water supply path to supply the water from a water supply source to the water discharge port therethrough; and a backflow check structure provided for the water supply path. The backflow check structure checks a backflow of the water running through the water supply path. The backflow check structure has: a water inlet port exposed to the air and directly communicating with the water discharge port; and a water outlet port to channel the water supplied from the water supply source toward the water inlet port. The water inlet port is arranged on a trajectory of the water running out through the water outlet port. The water that has passed through the water inlet port is channeled directly toward the water discharge port.
    Type: Application
    Filed: October 24, 2018
    Publication date: September 10, 2020
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasushi SATO, Masato MIYAMOTO
  • Patent number: 9711532
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Masato Miyamoto, Yuji Fukano
  • Publication number: 20170033121
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Masato Miyamoto, Yuji Fukano
  • Patent number: 9530781
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Masato Miyamoto, Yuji Fukano
  • Publication number: 20160181264
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Masato Miyamoto, Yuji Fukano
  • Publication number: 20160111439
    Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 21, 2016
    Inventors: Masanori Tsutsumi, Hiroshi Sasaki, Hiroyuki Ogawa, Michiaki Sano, Masato Miyamoto, Kensuke Yamaguchi, Seiji Shimabukuro
  • Patent number: 9305937
    Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Masanori Tsutsumi, Hiroshi Sasaki, Hiroyuki Ogawa, Michiaki Sano, Masato Miyamoto, Kensuke Yamaguchi, Seiji Shimabukuro
  • Patent number: 8870465
    Abstract: According to the present invention, there is provided a thrust bearing that includes a first race ring having a first race surface, a second race ring having a second race surface, a plurality of balls that is placed between the first race surface and the second race surface in a rollable manner, and a holder that holds the balls at equal intervals in a circumferential direction, wherein the holder is made of a synthetic resin, and a pocket interval is 2 to 5% of a diameter of the balls. Damage to the holder is prevented and the thrust bearing has a long life.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: October 28, 2014
    Assignee: NSK Ltd.
    Inventor: Masato Miyamoto
  • Patent number: 8702312
    Abstract: A conveyor bearing includes an inner ring fitted on and fixed to a shaft, a plurality of rolling elements arranged rollably on a raceway surface of the inner ring, an outer ring disposed of rotatably relative to the inner ring via the rolling elements, and a seal member to seal in a grease between the outer ring and the inner ring. The seal member has a plurality of seal lips and is mounted on at least one location on the bearing.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: April 22, 2014
    Assignee: NSK Ltd.
    Inventors: Manabu Yamada, Masato Miyamoto
  • Publication number: 20130188901
    Abstract: The present invention provides a thrust bearing that is incorporated in a hydraulic continuously variable transmission, and includes: an inner ring that comes into contact with a piston of a piston chamber of a variable capacity pump; an outer ring that is fixed to a swash plate; and a plurality of rolling elements that are held between the inner ring and the outer ring via a cage, wherein: a groove bottom thickness (Ti) of the inner ring is 40% or more of a ball diameter; a groove bottom thickness (Te) of the outer ring is 15% or more of the ball diameter; and a ratio of (Ti/Te) is is more than 1 and less than 3. Thereby, damage of the inner ring is prevented, and thus a thrust bearing for a hydraulic continuously variable transmission of a long service life is provided.
    Type: Application
    Filed: January 26, 2012
    Publication date: July 25, 2013
    Applicant: NSK LTD.
    Inventors: Chisato Tateyama, Masato Miyamoto
  • Publication number: 20130114921
    Abstract: According to the present invention, there is provided a thrust bearing that includes a first race ring having a first race surface, a second race ring having a second race surface, a plurality of balls that is placed between the first race surface and the second race surface in a rollable manner, and a holder that holds the balls at equal intervals in a circumferential direction, wherein the holder is made of a synthetic resin, and a pocket interval is 2 to 5% of a diameter of the balls. Damage to the holder is prevented and the thrust bearing has a long life.
    Type: Application
    Filed: January 26, 2012
    Publication date: May 9, 2013
    Applicant: NSK LTD.
    Inventor: Masato Miyamoto
  • Publication number: 20130001696
    Abstract: A gate electrode and an electrode for protective diode are coupled to each other. An insulating film below the electrode for protective diode makes a leak current flow between the electrode for protective diode and an electron transit layer and an electron supply layer when a voltage equal to or more than a given value is applied to the gate electrode. The given value is higher than a voltage by which a HEMT is on-operated and lower than a breakdown voltage of a gate insulating film.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 3, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Akiyama, Yoshiyuki Kotani, Toshihiro Wakabayashi, Masato Miyamoto
  • Patent number: 8193048
    Abstract: A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: June 5, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masato Miyamoto, Masanori Terahara
  • Publication number: 20110069917
    Abstract: A conveyor bearing includes an inner ring fitted on and fixed to a shaft, a plurality of rolling elements arranged rollably on a raceway surface of the inner ring, an outer ring disposed of rotatably relative to the inner ring via the rolling elements, and a seal member to seal in a grease between the outer ring and the inner ring. The seal member has a plurality of seal lips and is mounted on at least one location on the bearing.
    Type: Application
    Filed: May 27, 2008
    Publication date: March 24, 2011
    Applicant: NSK LTD.
    Inventors: Manabu Yamada, Masato Miyamoto
  • Publication number: 20080237784
    Abstract: A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masato MIYAMOTO, Masanori TERAHARA
  • Patent number: 5524821
    Abstract: A method and apparatus for generating a high-pressure fluid jet which preferably draws a material, such as an additive, into the fluid jet. A working pressure of the fluid is increased to generate a high-pressure fluid. The high-pressure fluid is stored within a high-pressure chamber of an accumulator. The stored high-pressure fluid is discharged through a discharge port of the accumulator. The pressure of the high-pressure fluid within the high-pressure chamber is maintained by decreasing the volume of the high-pressure gas chamber as the fluid passes through the discharge port. The high-pressure fluid is then transported into an injection nozzle for forming a high-pressure fluid jet. Within the injection nozzle, a material is combined with the high-pressure fluid jet. The combined fluid and material jet is then discharged from the injection nozzle.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: June 11, 1996
    Assignee: Jetec Company
    Inventors: Gene G. Yie, Masato Miyamoto
  • Patent number: 5420046
    Abstract: A method for manufacturing an optically triggered lateral thyristor is to form an anode region by providing a first opening in an insulating layer formed on a semiconductor substrate, a diffusion layer by providing a second opening in the insulating layer to be spaced from the anode region, a base-forming region by providing a third opening in the insulating layer externally adjacent to the second opening, and a base region and simultaneously a cathode region by means of double diffusion through the third opening, the base region having a lateral width determined by a diffusion difference between the base and cathode regions for effective minimization of the width.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: May 30, 1995
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Sigeo Akiyama, Fumio Kato, Kiyoshi Hosotani, Masato Miyamoto