Abstract: A flip-flop circuit consists of a conventional pulse-drive flip-flop plus a clock driver and a local pulse generator that generates a pulse signal according to the output of the clock driver. The flip-flop circuits of this kind are used to form, for example, a shift register in which the clock drivers are connected in series from the last stage toward the first stage. The clock driver in the last stage receives a clock signal, which is successively supplied to the flip-flop circuits from the one in the last stage toward the one in the first stage. This arrangement prevents a data-pass-through problem, assures a sharp waveform of pulse signals, and reduces the size of each clock driver. This type of flip-flop circuits may be used to form logic circuits such as N-bit registers and N-bit shift registers.

Abstract: In an instruction distribution control device for parallel execution of instructions for use in a superscalar parallel processor, the control device comprises an instruction distribution starting position pointer register, an instruction distribution enable/disable signal generating circuit, and an updating circuit. The distribution starting position pointer register indicates from which instruction of N (>1) instructions the distribution is to be started. The instruction distribution enable/disable signal generating circuit generates signals for determining whether the instructions may or may not be distributed to instruction executing arithmetic units on the basis of the contents of the instruction distribution starting position pointer register and signals indicating the results of dependence analysis for examining resource conflict.

Abstract: Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality of data; and a bypass control unit for comparing an operation result outputted from the arithmetic operation unit and a data outputted from the register control unit, selecting a data to be an object of the next arithmetic operation, and transferring the selected data to the arithmetic operation unit through a suitable bypass.

Abstract: A low-cost high-speed multiplier comprises a first register for holding a multiplier; a second register for holding a multiplicand; a partial product generator for scanning the multiplier held in the first register to generate three partial products of the multiplicand held in the second register; a 4-input adder for finding the sum of the three partial products and a fourth number; a shift register for holding and shifting the sum; and a unit for returning the shifted sum except a shifted-out portion of the sum to an input of the 4-input adder. This arrangement can process three partial products in one time of addition.

Abstract: A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainde

Abstract: A method for forming in a short time master-slice integrated circuits of high reliability, which circuits comprise diffusion layers and polysilicon layers which form transistor elements, and a plurality of metal wiring layers formed for realizing desired circuits, with insulating layers interposed between every adjacent two of the wiring layers. The methods comprises a first wiring process in which a master slice is provided by forming a predetermined number of metal layers in a wafer, and a second wiring process in which further metal wiring layers, to be customized so as to have logical functions required by a user, are formed on the first-mentioned metal wiring layers. The inner-most metal wiring layer of all the metal layers is used as wide power source line which is almost free from electro or stress migration.

Abstract: A logic arithmetic circuit comprising first through sixth transistors, the first through third being P-channel transistors and the fourth through sixth being N-channel transistors. The gates of the first and sixth transistors are supplied by a synchronizing signal; the gates of the second and fifth are supplied by a first operand signal; and the gates of the third and fourth are supplied by a second operand signal. Respective current paths are provided between the first and the sixth transistors through the second and fourth transistors and through the third and fifth transistors with the output signal taken at the connecting point of the fourth and fifth transistors with the sixth transistor.