Patents by Inventor Masato Nakakita
Masato Nakakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11916397Abstract: A combined electric power generations' supply system includes an AC power generator that supplies power by off grid independent operation, a DC power supply device, an inverter that converts DC power output by the DC power supply device into AC power. The rotation calculation unit calculates a value relating to a rotation of a rotor when driving the virtual power generator according to an active power command based on a rotor model calculates a value relating to the rotation of the rotor of the virtual power generator and the active power command. The output determination unit determines values relating to an active power and a reactive power to be output to the inverter based on the calculated value relating to the rotation. The modulation control unit performs control of a pulse width modulation of the inverter based on the determined value relating to the active power and reactive power.Type: GrantFiled: August 29, 2019Date of Patent: February 27, 2024Assignee: MITSUBISHI HEAVY INDUSTRIES ENGINE & TURBOCHARGER, LTD.Inventors: Osamu Nakakita, Masayuki Tanaka, Hiroyuki Suzuki, Hirotaka Uehara, Masato Mitsuhashi, Fujio Eguchi
-
Patent number: 7646245Abstract: An amplifier includes: a single-stage or multiple-stage variable gain amplifier that amplifies an input signal with a controlled gain; a AGC control circuit that detects the peak level of a signal outputted from the variable gain amplifier in the final stage, converts the resultant signal to a digital signal, and outputs an AGC control signal for controlling the gain of the variable gain amplifier based on the converted digital signal; an EVR control circuit that outputs an EVR control signal according to a signal of setting an attenuation value or an amplification value for EVR inputted from an electronic variable resistor control terminal; and a gain control circuit that controls the gain of the variable gain amplifier in accordance with at least one of the AGC control signal and the EVR control signal. The occurrence of “popping” sounds caused by differences in DC voltage due to switching between an AGC circuit and an electronic variable resistor circuit can be suppressed.Type: GrantFiled: October 22, 2007Date of Patent: January 12, 2010Assignee: Panasonic CorporationInventors: Masato Nakakita, Makoto Yamamoto
-
Publication number: 20080129387Abstract: An amplifier includes: a single-stage or multiple-stage variable gain amplifier that amplifies an input signal with a controlled gain; a AGC control circuit that detects the peak level of a signal outputted from the variable gain amplifier in the final stage, converts the resultant signal to a digital signal, and outputs an AGC control signal for controlling the gain of the variable gain amplifier based on the converted digital signal; an EVR control circuit that outputs an EVR control signal according to a signal of setting an attenuation value or an amplification value for EVR inputted from an electronic variable register control terminal; and a gain control circuit that controls the gain of the variable gain amplifier in accordance with at least one of the AGC control signal and the EVR control signal. The occurrence of “popping” sounds caused by differences in DC voltage due to switching between an AGC circuit and an electronic variable register circuit can be suppressed.Type: ApplicationFiled: October 22, 2007Publication date: June 5, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masato Nakakita, Makoto Yamamoto
-
Patent number: 7319420Abstract: A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n?1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.Type: GrantFiled: January 25, 2006Date of Patent: January 15, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masato Nakakita, Fumihito Inukai, Hitoshi Kobayashi
-
Publication number: 20070159557Abstract: A semiconductor integrated circuit includes an audio signal amplifier and a video signal amplifier built in a single semiconductor chip, the audio signal amplifier and the video signal amplifier being configured to receive a supply of a positive power supply voltage and a negative power supply voltage. The semiconductor integrated circuit further includes a negative voltage generation circuit that generates the negative power supply voltage and supplies the negative power supply voltage to the audio signal amplifier and the video signal amplifier and a limit circuit that limits an amplitude of a signal input to the audio signal amplifier to a range free from an influence of a fluctuation in the negative power supply voltage supplied by the negative voltage generation circuit. Adverse effects on an audio signal due to a fluctuation of a negative voltage occurring in synchronization with the vertical period of a video signal can be suppressed with a simple additional circuit.Type: ApplicationFiled: December 28, 2006Publication date: July 12, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masato Nakakita, Makoto Yamamoto, Toshinobu Nagasawa
-
Publication number: 20060164274Abstract: A cascade-type variable-order delta-sigma modulator with low power consumption that can change the number of stages of the quantization loops, which are connected in a cascade configuration, to an optimum number depending on peripheral circuitries in a configuration as simple as possible. The present invention includes first to nth stages of delta-sigma modulating type quantization loops (n is an integer equal to or more than 2) connected in a cascade configuration, and a noise rejecting circuit. Each quantization loop quantizes an input signal, outputs the quantization result, and feeds back the quantization result to itself. The noise rejecting circuit rejects a quantization noise of the first stage of quantization loop, and comprises (n?1) selectors for activating and de-activating the respective output signals of the second and succeeding stages of the quantization loops in compliance with the control signal.Type: ApplicationFiled: January 25, 2006Publication date: July 27, 2006Inventors: Masato Nakakita, Fumihito Inukai, Hitoshi Kobayashi