Abstract: According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.

Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.

Abstract: According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.

Abstract: It is intended to provide a comparator circuit which uses a switched capacitor and has a small circuit size. An input INA is supplied to positive input terminals of comparators Com1 and Com2 through a capacitor Ca by means of a switch SW1. An input INB is supplied to a negative input terminal of the comparator Com1 through a capacitor Cb1 by means of a switch SW2, and in addition, is supplied to a negative input terminal of the comparator Com2 after being inverted through the use of a capacitor Cb2 by means of switches SW3 and SW4. Outputs from the comparators Com1 and Com2 are input to an exclusive OR circuit EXOR, which outputs a result of judgment as to whether or not the input INA is within the range extending between the positive input INB and the negative input INB.

Abstract: A trap filter comprises a delay circuit made up of switched capacitors for delaying an input signal and outputting a delay signal, and an adding circuit for adding the input signal and the delay signal.

Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors and which is charged/discharged by turning on/off gates of the charging and the discharging MOS transistors, and wherein the plurality of switched capacitor units are connected such that the input signal is input in common to each of drains of the charging MOS transistors and such that the capacitive elements are charged as well as such that the capacitive elements are discharged to allow the output signal to be output from each of drains of the discharging MOS transistors; and a switching control unit that performs on/off control of each of gates of the charging and the discharging MOS transistors, to cause each of the

Abstract: A random number generator comprising a plurality of pseudo random number generating units that can respectively output random numbers in specified pseudo random number systems, an output random number generating unit that generates output random numbers based on outputs from a plurality of pseudo random number generating units, a physical random number generator that generates physical random numbers, and a switching unit for switching between the necessity and the non-necessity of updating output values from pseudo random number generating units based on physical random numbers generated by the physical random number generator. Based on which pseudo random number system an output random number is generated is randomly switched based on a physical random number, making it very difficult to predict a random number compared with a conventional one.

Abstract: A video signal processing apparatus receives a video signal containing at least a luminance signal and a color difference signal. A trap filter attenuates a frequency band of the color difference signal to separate the luminance signal from the video signal. A bandpass filter attenuates a frequency band of the luminance signal to separate the color difference signal from the video signal. The trap filter is constituted by a switched capacitor filter that outputs the luminance signal with a delay time equivalent to a time difference between a delay time of the processing performed in a succeeding luminance signal processing circuit and a delay time of the processing performed in a color difference signal processing circuit. With this arrangement, the circuit scale of a filter circuit can be reduced and frequency characteristics of the filter can be stabilized.

Abstract: A random number generation device comprises a pseudo random number generation section that is capable of outputting random numbers of a plurality of different pseudo random number sequences, a physical random number generation section for generating physical random numbers, and a switching section for switching the pseudo random number sequence of random numbers output by the pseudo random number generation section on the basis of the physical random numbers generated by the physical random number generation section, where the output of the pseudo random number generation section is used as output random numbers. Since the plurality of different pseudo random number sequences are switched and output according to the physical random numbers, predictability of the random numbers can be reduced in comparison to a conventional random number generation device that uses only pseudo random numbers.

Abstract: A trap filter comprises a delay circuit made up of switched capacitors for delaying an input signal and outputting a delay signal, and an adding circuit for adding the input signal and the delay signal.

Abstract: In a surround circuit, an audio signal or another analog signal is converted to a digital signal by an A/D conversion circuit (11) and stored in a memory (12). Subsequently, the digital signal read from the memory (12) is converted to an analog signal by a D/A conversion circuit (13). The memory (12) then functions as a delay circuit, and a delayed audio signal is obtained. By superimposing the obtained delay signal to the transmitted audio signal, a surround sound is obtained. Here, a sampling frequency of either one of the A/D conversion circuit (11) and the D/A conversion circuit (13) is changed with an elapse of time, which leads the sampling frequency of the A/D conversion circuit (11) to differ from that of the D/A conversion circuit (13), and the frequency of an output signal of the D/A conversion circuit (13) differs from that of the audio signal transmitted to the A/D conversion circuit (11). Consequently, a delay signal in which the frequency of the input audio signal is dispersed can be obtained.

Abstract: Pulse signals indicating up or down of a time constant are received and counted. When a time-out occurs, a time constant change signal is output. At up counting, when input signal is low, the flip-flop 80 of each bit is forcibly set to 1. Then, an up counter consisting of the high-order two bits (control bits) is provided. A time constant of a variable integrator is changed in response to output of the high-order two bits, so that the time constant can be changed rapidly. On the other hand, if the input signal is high, a 5-bit down counter is provided. Thus, the time constant of the variable integrator can be changed gently.

Abstract: An adder 22, a quantizer 20, and a variable integrator 24 execute A/D conversion and the result is stored in a memory 12. A time constant of the variable integrator at this time is controlled by a time constant controller 25. On the other hand, data from the memory is integrated by a variable integrator 28 to provide an analog signal. At this time, control data of the time constant controller 25 is transferred via a memory 32 to a time constant controller 33, which then uses the transferred control data to control the time constant of the variable integrator 28. When a mode is changed, switches 34 and 35 are turned off. Therefore, a signal with no input can be written into the memory 12 for initializing the memory 12.

Abstract: A plurality of delay time data can easily be obtained. A data input unit 32 successively writes data into a memory 30. A data output unit 36 outputs data from six areas a-f in the memory 30 in the parallel manner. Selection units SW1 and SW2 successively select and output data read out from the six areas a-f in the memory 30. Locations to be read are shifted from one another by the selection units SW1 and SW2 to output data from different memory locations. Thus, a plurality of data which are different in time between write and readout operations (i.e., different delay times) can be obtained simultaneously.

Abstract: The balance of the volumes in right and left channels in a stereo play back system is controlled. The amount of attenuation of an attenuator provided in each channel is controlled. When the levels of right and left stereo signals are judged to be approximately the same, an oscillator is permitted to oscillate and the pulses from the oscillator are counted by a counter. In accordance with a voltage signal which corresponds to the level ratio of the right and left stereo signals, whether the counter must count upwards or downwards is determined. The balance is controlled in accordance with the amount of attenuation of each attenuator which is determined in accordance with the decoded count value. The completion of the control is detected when the level ratio of the right and left stereo signals alternately change after they become substantially equal, and the control is automatically finished.

Abstract: A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter.