Abstract: In a semiconductor device having a first insulator layer on a semiconductor substrate and accumulation electrode layers overlying the first insulator layer, second insulator layers overlie predetermined areas of the first insulator layer and side electrode surfaces of the accumulation electrode layers. Each of the second insulator layers has a primary dielectric constant. A dielectric layer overlies upper surfaces of the accumulation electrode layers and the second insulator layers and has a secondary dielectric constant which is higher than the primary dielectric constant. An opposed electrode layer overlies the dielectric layer.

Abstract: A semiconductor memory device including a plurality of memory cells of one-transistor and one-capacitor type is disclosed. The memory cells are formed respectively in active regions each isolated from peripheral active regions by trench isolation regions in a first direction and by isolation gate conductors supplied with a bias potential in a second direction perpendicular to the first direction. Each of the trench isolation regions comprises a trench selectively formed in a semiconductor substrate and a first insulating film filling the trench and each of the isolation conductors is formed simultaneously with word lines and is thus isolated from the substrate by a second insulating film which has the same thickness as the gate insulating film of the cell transistor.

Abstract: A method of manufacturing a semiconductor device in which a portion of a monocrystalline silicon layer protruded from a surface of an insulating member is polished up to the surface by a chemical-mechanical polishing is disclosed. A polycrystalline silicon layer and a leveling material are formed in sequence on the protruded portion of the monocrystalline silicon layer and on an exposed part of the surface of the insulating member, and a reactive ion etching and the chemical-mechanical polishing are carried out.