Patents by Inventor Masato Shigematsu
Masato Shigematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10923610Abstract: Provided is a solar cell that can suppress loss of power generation performance of a solar cell module when shaded and a solar cell module having the solar cell. An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: GrantFiled: November 30, 2016Date of Patent: February 16, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
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Patent number: 10784396Abstract: An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: GrantFiled: December 29, 2016Date of Patent: September 22, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
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Publication number: 20200164623Abstract: An object of the present invention is to provide a cellulose-based sheet which has excellent transparency, and exhibits excellent adhesiveness when thermally press-adhered. The sheet includes a laminate including a layer formed of a cellulose-based material and a layer formed of a thermoplastic elastomer. Each of molecules forming the thermoplastic elastomer has both a rubber component having entropy elasticity and a molecule-constraining component for preventing plastic deformation.Type: ApplicationFiled: May 9, 2018Publication date: May 28, 2020Applicant: DAICEL CORPORATIONInventors: Tomohiro HASHIZUME, Masato SHIGEMATSU, Yugo TAKANO
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Patent number: 10181540Abstract: An aspect of the invention provides a solar cell that comprises a semiconductor substrate having a light-receiving surface and a rear surface; a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type, the first semiconductor layer and the second semiconductor layer being formed on the rear surface, and a trench formed in the rear surface, wherein the first semiconductor layer is formed on the rear surface in which the trench is not formed, and the second semiconductor layer is formed on a side surface of the trench in an arrangement direction in which the first semiconductor layer and the second semiconductor layer are alternately arranged and on a bottom surface of the trench.Type: GrantFiled: July 25, 2012Date of Patent: January 15, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Daisuke Ide, Takahiro Mishima, Masato Shigematsu, Toshiaki Baba, Hiroyuki Mori, Mitsuaki Morigami, Yuji Hishida, Hitoshi Sakata, Ryo Goto
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Patent number: 10014420Abstract: A solar cell includes: a semiconductor substrate having a light-receiving surface and a back surface; a first-conductivity-type first semiconductor layer on the back surface; a second-conductivity-type second semiconductor layer on the back surface; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; and an insulating layer in a boundary region between a first-conductivity-type region of the first semiconductor layer and a second-conductivity-type region of the second semiconductor layer. The insulating layer has an inclined side surface adjacent the second-conductivity-type region inclined such that the thickness of the insulating layer decreases with decreasing distance from the second-conductivity-type region.Type: GrantFiled: July 27, 2016Date of Patent: July 3, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Masato Shigematsu, Naofumi Hayashi
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Patent number: 9968492Abstract: A bloomed fiber material (bloomed tow) is manufactured through a process including: spreading a crimped tow in its width direction by a preliminary blooming device; performing primary blooming to bloom the tow by a primary blooming device; dividing the tow into at least two divided tows by a dividing device; cutting a parting between the divided tows by a cutting device; and performing secondary blooming to bloom the divided tows by a secondary blooming device.Type: GrantFiled: December 26, 2014Date of Patent: May 15, 2018Assignee: DAICEL CORPORATIONInventors: Shingo Nagata, Masato Shigematsu, Toshiyuki Morioka
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Publication number: 20180033898Abstract: A solar cell includes: a first semiconductor layer provided in a first area on a principal surface; an insulating layer provided on the first semiconductor layer in an insulating area adjacent to a second area; a second semiconductor layer provided to extend across the principal surface in the second area and the insulating layer in the insulating area; a transparent conductive layer provided on the first semiconductor layer and the second semiconductor layer; a first metal electrode provided in the first area; and a second metal electrode provided in the second area. The second metal electrode is formed to have an overhanging portion projecting to approach the first metal electrode with increasing distance from the principal surface and such that a gap from the first metal electrode is positioned in the insulating area. The transparent conductive layer is provided to avoid an isolation area aligned with the gap.Type: ApplicationFiled: September 26, 2017Publication date: February 1, 2018Inventors: Masato SHIGEMATSU, Yasufumi TSUNOMURA
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Patent number: 9705027Abstract: A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.Type: GrantFiled: May 26, 2016Date of Patent: July 11, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Naofumi Hayashi, Mitsuaki Morigami, Masato Shigematsu, Takahiro Mishima
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Publication number: 20170194524Abstract: Provided is a solar cell that can suppress loss of power generation performance of a solar cell module when shaded and a solar cell module having the solar cell. An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: ApplicationFiled: November 30, 2016Publication date: July 6, 2017Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
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Publication number: 20170179315Abstract: An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: ApplicationFiled: December 29, 2016Publication date: June 22, 2017Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
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Publication number: 20170020749Abstract: A hydrophilized cellulose acetate tow band according to the present invention includes a crimped cellulose acetate tow band, and a hydrophilizing component having an HLB value of 16 or more. The cellulose acetate tow band includes a cellulose acetate having a degree of substitution of 2.0 to 2.6. The cellulose acetate tow band has a total denier of 10000 to 40000 and is crimped in a number of crimps of 30 to 60 per inch. The hydrophilizing component is impregnated on the cellulose acetate tow band in an amount of 0.2 to 2 weight percent relative to the cellulose acetate tow band. The hydrophilized cellulose acetate tow band may further include a textile oil, where the textile oil is impregnated on the crimped cellulose acetate tow band in an amount of 0.2 to 2 weight percent relative to the cellulose acetate tow band, in addition to the hydrophilizing component having an HLB value of 16 or more.Type: ApplicationFiled: April 1, 2015Publication date: January 26, 2017Applicant: DAICEL CORPORATIONInventors: Toshikazu NAKAMURA, Masato SHIGEMATSU
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Publication number: 20160333507Abstract: A bloomed fiber material (bloomed tow) is manufactured through a process including: spreading a crimped tow in its width direction by a preliminary blooming device; performing primary blooming to bloom the tow by a primary blooming device; dividing the tow into at least two divided tows by a dividing device; cutting a parting between the divided tows by a cutting device; and performing secondary blooming to bloom the divided tows by a secondary blooming device.Type: ApplicationFiled: December 26, 2014Publication date: November 17, 2016Applicant: DAICEL CORPORATIONInventors: Shingo NAGATA, Masato SHIGEMATSU, Toshiyuki MORIOKA
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Publication number: 20160336464Abstract: A solar cell includes: a semiconductor substrate having a light-receiving surface and a back surface; a first-conductivity-type first semiconductor layer on the back surface; a second-conductivity-type second semiconductor layer on the back surface; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; and an insulating layer in a boundary region between a first-conductivity-type region of the first semiconductor layer and a second-conductivity-type region of the second semiconductor layer. The insulating layer has an inclined side surface adjacent the second-conductivity-type region inclined such that the thickness of the insulating layer decreases with decreasing distance from the second-conductivity-type region.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Masato SHIGEMATSU, Naofumi HAYASHI
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Publication number: 20160268470Abstract: A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.Type: ApplicationFiled: May 26, 2016Publication date: September 15, 2016Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Naofumi HAYASHI, Mitsuaki MORIGAMI, Masato SHIGEMATSU, Takahiro MISHIMA
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Patent number: 9362426Abstract: This photoelectric conversion device (10) is provided with: an n-type monocrystalline silicon substrate (21); an IN layer (25) and an IP layer (26) formed on the back surface of the n-type monocrystalline silicon substrate (21); an n-side electrode (40) containing an n-side underlayer (43), an n-side primary conductive layer (44), and an n-side protective layer (45); and a p-side electrode (50) containing a p-side underlayer (53), a p-side primary conductive layer (54), and a p-side protective layer (55). The n-side primary conductive layer (44) is formed in a manner so as not to cover the lateral surface of the n-side underlayer (43), and is covered at the lateral surface by the n-side protective layer (45). The p-side electrode (50) is formed in such a manner the lateral surface of the p-side underlayer (53) is not covered, and the lateral surface is covered by the p-side protective layer (55).Type: GrantFiled: September 20, 2013Date of Patent: June 7, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Ryo Goto, Satoru Shimada, Masato Shigematsu, Hitoshi Sakata, Daisuke Ide
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Patent number: 9252301Abstract: A solar cell includes semiconductor substrate of a first conductivity type; first semiconductor layer having a first conductivity type; second semiconductor layer having a second conductivity type; first electrode; second electrode; and insulating layer. First semiconductor layer and second semiconductor layer are formed on rear surface. When one end portion of insulating layer which is formed on first semiconductor layer and which is on a side close to first electrode is defined as first insulating-layer end portion and another end portion of insulating layer on a side close to second electrode is defined as second insulating-layer end portion in arrangement direction x, a distance from end point of second-semiconductor-layer end portion in contact with rear surface to second insulating-layer end portion in arrangement direction x is shorter than a distance from end point to first insulating-layer end portion in arrangement direction x.Type: GrantFiled: August 24, 2012Date of Patent: February 2, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Mitsuaki Morigami, Yuji Hishida, Daisuke Ide, Hitoshi Sakata, Takahiro Mishima, Hiroyuki Mori, Masato Shigematsu
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Patent number: 9204669Abstract: A cigarette filter comprises a cellulose ester tow and a cellulose acetate particle dispersed in the cellulose ester tow, and the cellulose acetate particle has the following particle size: not less than 90% by weight of the cellulose acetate particle pass through a sieve having an aperture size of 1.7 mm and fail to pass through a sieve having an aperture size of 0.10 mm, and these sieves are in accordance with JIS Z8801-1 2006.Type: GrantFiled: October 25, 2011Date of Patent: December 8, 2015Assignee: Daicel CorporationInventors: Hiroki Taniguchi, Masato Shigematsu, Takashi Ikebe, Toshiyuki Morioka
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Patent number: D828292Type: GrantFiled: December 20, 2016Date of Patent: September 11, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu
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Patent number: D894823Type: GrantFiled: July 31, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPETY MANAGEMENT CO., LTD.Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu
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Patent number: D894824Type: GrantFiled: July 31, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naoki Yoshimura, Keiichiro Masuko, Daisuke Fujishima, Masato Shigematsu