Patents by Inventor Masato Suga

Masato Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040262640
    Abstract: a semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum wire width which is substantially equal to the first minimum wire width, formed on a second wiring layer which differs from the first wiring layer and extending in a diagonal direction in relation to the orthogonal wire; and a via having a size which is no greater than the first or second wire width, formed at point at which the orthogonal wire and diagonal wire overlap so as to connect the orthogonal wire and diagonal wire, wherein one of the diagonal wire and orthogonal wire includes an enlarged wire width region in the position at which the via is formed, the wire width of the enlarged wire width region being enlarged beyond the first or second minimum wire width.
    Type: Application
    Filed: March 16, 2004
    Publication date: December 30, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Masato Suga
  • Publication number: 20040188844
    Abstract: A first dummy pattern is arranged in the region allowed to generate the first dummy pattern, after that, the second dummy pattern is generated in the region not allowed to generate the first dummy pattern but allowed to generate the second dummy pattern to thereby enable to arrange the dummy patterns in an efficient manner in the wiring layer, so that the wiring density can be improved and differences in the wiring densities can be reduced.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 30, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masato Suga, Satoshi Otsuka
  • Publication number: 20040188843
    Abstract: A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.
    Type: Application
    Filed: February 13, 2004
    Publication date: September 30, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Shigetoshi Wakayama, Mutsuaki Kai, Hiroyuki Kato, Masato Suga
  • Publication number: 20040188849
    Abstract: Capacitance generated by a dummy pattern can be reduced without lowering wiring density by arranging the dummy pattern on one wiring layer in a manner responding to an actual pattern or the dummy pattern on the other wiring layer, whereby at least one of the following can be improved: distances between dummy patterns on different wiring layers, overlapped areas of dummy patterns, and such side length of the dummy pattern as opposed to the actual pattern on the same wiring layer.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 30, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Masato Suga
  • Publication number: 20030174007
    Abstract: A semiconductor integrated circuit includes first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.
    Type: Application
    Filed: January 15, 2003
    Publication date: September 18, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Masato Suga
  • Patent number: 6319753
    Abstract: A semiconductor device having lead terminals bent in a J-shape is disclosed. A radiating plate having a recess formed on an outer peripheral portion thereof is exposed to a lower face of a resin member and free ends of outer portions of the lead terminals are positioned in the recess of the radiating plate. The free ends of the outer portions of the lead terminals and the recess of the radiating plate are isolated from each other by projections of the resin member. Since the radiating plate is exposed to the lower face of the resin member, the heat radiating property is high whereas the radiating plate and the lead terminals are not short-circuited to each other at all.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
  • Patent number: 6242797
    Abstract: A semiconductor device having a pellet mounted on a radiating plate thereof is disclosed. The radiating plate is formed in such a shape that a central portion thereof is positioned higher than both end portions thereof. A pellet is mounted on a lower face of the central portion of the radiating plate, and an upper face of the central portion of the radiating plate is exposed to the top of a resin member. Since the upper face of the central portion of the radiating plate which has the pellet mounted on the lower face thereof is exposed from the resin member, heat generated by the pellet can be radiated efficiently.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: June 5, 2001
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
  • Patent number: 6177720
    Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: January 23, 2001
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
  • Patent number: 6175150
    Abstract: A plastic-encapsulated semiconductor device is provided, which is capable of efficient heat dissipation without upsizing while preventing the moisture from reaching an IC chip. This device is comprised of an electrically-conductive island having a chip-mounting area, an IC chip fixed on the chip-mounting area of the island, leads electrically connected to bonding pads of the chip through bonding wires, a plastic package for encapsulating the island, the chip, the bonding wires, and inner parts of the leads. The package has an approximately flat bottom face. Outer parts of the leads are protruded from the package and are located in approximately a same plane as the bottom face of the package. The island has an exposition part exposed from the package at a location excluding the chip-mounting area. A lower face of the exposition part of the island is located in approximately a same plane as the bottom face of the package. The chip and the chip-mounting area of the island are entirely buried in the package.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: January 16, 2001
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Tooru Kitakoga, Kazuhiro Tahara
  • Patent number: 6165818
    Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: December 26, 2000
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara
  • Patent number: 6150715
    Abstract: A semiconductor device of the present invention comprises a semiconductor pellet, a radiation plate mounted with the semiconductor pellet, a plurality of lead terminals electrically connected with the semiconductor pellet, and a resin member for encapsulating the above items. The resin member has a first surface and a second surface, and the radiation plate has a first portion exposed to the outside from the first surface of the resin member and a second portion exposed to the outside from the second surface of the resin member.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: November 21, 2000
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Kazunari Sato, Kunihiko Tsubota, Yoshikazu Nishimura, Toshiaki Nishibe, Kazuhiro Tahara, Masato Suga, Toru Kitakoga, Tatsuya Miya, Keita Okahira
  • Patent number: 6104086
    Abstract: A semiconductor device having lead terminals bent in a J-shape is disclosed. A radiating plate having a recess formed on an outer peripheral portion thereof is exposed to a lower face of a resin member and free ends of outer portions of the lead terminals are positioned in the recess of the radiating plate. The free ends of the outer portions of the lead terminals and the recess of the radiating plate are isolated from each other by projections of the resin member. Since the radiating plate is exposed to the lower face of the resin member, the heat radiating property is high whereas the radiating plate and the lead terminals are not short-circuited to each other at all.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: August 15, 2000
    Assignee: NEC Corporation
    Inventors: Seiji Ichikawa, Takeshi Umemoto, Toshiaki Nishibe, Kazunari Sato, Kunihiko Tsubota, Masato Suga, Yoshikazu Nishimura, Keita Okahira, Tatsuya Miya, Toru Kitakoga, Kazuhiro Tahara