Patents by Inventor Masato Sugita
Masato Sugita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230343371Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: July 5, 2023Publication date: October 26, 2023Applicant: KIOXIA CORPORATIONInventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
-
Patent number: 11735230Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: December 30, 2021Date of Patent: August 22, 2023Assignee: Kioxia CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Publication number: 20220122640Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: December 30, 2021Publication date: April 21, 2022Applicant: Kioxia CorporationInventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
-
Patent number: 11244708Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: October 22, 2020Date of Patent: February 8, 2022Assignee: Kioxia CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Publication number: 20210043235Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Applicant: Toshiba Memory CorporationInventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
-
Patent number: 10847190Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: January 8, 2020Date of Patent: November 24, 2020Assignee: Toshiba Memory CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Publication number: 20200143848Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Applicant: Toshiba Memory CorporationInventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
-
Patent number: 10566033Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: May 28, 2019Date of Patent: February 18, 2020Assignee: Toshiba Memory CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Publication number: 20190279686Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Applicant: Toshiba Memory CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Patent number: 10339981Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: July 25, 2018Date of Patent: July 2, 2019Assignee: Toshiba Memory CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Patent number: 10276517Abstract: A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls.Type: GrantFiled: September 4, 2017Date of Patent: April 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Gen Watari, Masato Sugita
-
Publication number: 20180330764Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: July 25, 2018Publication date: November 15, 2018Applicant: Toshiba Memory CorporationInventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
-
Publication number: 20180277498Abstract: A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls.Type: ApplicationFiled: September 4, 2017Publication date: September 27, 2018Inventors: Gen WATARI, Masato SUGITA
-
Patent number: 10056119Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: July 11, 2017Date of Patent: August 21, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Patent number: 9901009Abstract: According to one embodiment, a semiconductor memory device includes a case, a first substrate, an element, and a first heat conduction member. The first substrate is provided in the case and includes a first face. The element is provided on the first face. The first heat conduction member is disposed at least between the element and the case. The element includes a second substrate, a control unit, and a storage unit. The second substrate includes a second face attached to the first face and a third face located opposite to the second face. The control unit and the storage unit are provided on the third face. The first heat conduction member covers the third face and the control unit and is disposed in a state in which the first heat conduction member is held between and compressed by the third face, the control unit, and the case.Type: GrantFiled: September 11, 2015Date of Patent: February 20, 2018Assignee: Toshiba Memory CorporationInventors: Masato Sugita, Masayasu Kawase
-
Publication number: 20170309313Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: July 11, 2017Publication date: October 26, 2017Applicant: Toshiba Memory CorporationInventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
-
Patent number: 9721621Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: August 12, 2016Date of Patent: August 1, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
-
Publication number: 20160351232Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: August 12, 2016Publication date: December 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
-
Publication number: 20160307818Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface, a hole formed through the first and second surfaces of the substrate, a semiconductor element disposed on the first surface to cover the hole, a housing in which the substrate and the semiconductor element are housed, and a heat conduction member disposed in the hole, such that heat generated by the semiconductor element is transferred through the heat conduction member towards a portion of the housing facing the second surface of the substrate.Type: ApplicationFiled: August 27, 2015Publication date: October 20, 2016Inventors: Masayasu KAWASE, Masato SUGITA
-
Patent number: 9449654Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: July 10, 2014Date of Patent: September 20, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura