Patents by Inventor Masato Sugita

Masato Sugita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230343371
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: July 5, 2023
    Publication date: October 26, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
  • Patent number: 11735230
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Kioxia Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20220122640
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: December 30, 2021
    Publication date: April 21, 2022
    Applicant: Kioxia Corporation
    Inventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
  • Patent number: 11244708
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Kioxia Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20210043235
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
  • Patent number: 10847190
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20200143848
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
  • Patent number: 10566033
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20190279686
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10339981
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10276517
    Abstract: A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: April 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Gen Watari, Masato Sugita
  • Publication number: 20180330764
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: July 25, 2018
    Publication date: November 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
  • Publication number: 20180277498
    Abstract: A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls.
    Type: Application
    Filed: September 4, 2017
    Publication date: September 27, 2018
    Inventors: Gen WATARI, Masato SUGITA
  • Patent number: 10056119
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 9901009
    Abstract: According to one embodiment, a semiconductor memory device includes a case, a first substrate, an element, and a first heat conduction member. The first substrate is provided in the case and includes a first face. The element is provided on the first face. The first heat conduction member is disposed at least between the element and the case. The element includes a second substrate, a control unit, and a storage unit. The second substrate includes a second face attached to the first face and a third face located opposite to the second face. The control unit and the storage unit are provided on the third face. The first heat conduction member covers the third face and the control unit and is disposed in a state in which the first heat conduction member is held between and compressed by the third face, the control unit, and the case.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: February 20, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Masayasu Kawase
  • Publication number: 20170309313
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 26, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
  • Patent number: 9721621
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Publication number: 20160351232
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: August 12, 2016
    Publication date: December 1, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
  • Publication number: 20160307818
    Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface, a hole formed through the first and second surfaces of the substrate, a semiconductor element disposed on the first surface to cover the hole, a housing in which the substrate and the semiconductor element are housed, and a heat conduction member disposed in the hole, such that heat generated by the semiconductor element is transferred through the heat conduction member towards a portion of the housing facing the second surface of the substrate.
    Type: Application
    Filed: August 27, 2015
    Publication date: October 20, 2016
    Inventors: Masayasu KAWASE, Masato SUGITA
  • Patent number: 9449654
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura