Patents by Inventor Masato Teratani

Masato Teratani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7203357
    Abstract: Image data of a target pixel and peripheral pixels are stored in a memory. Using a most significant bit extractor circuit, 4 most significant bits of data are extracted from each image data. A histogram circuit generates a histogram of the extracted 4-bit data. Referring to the histogram, a data processor circuit (17) replaces the image data of the target pixel with a maximum value of the numbers of pixels having the same level and outputs the processed data. Then, a digit-complementing circuit converts the data output from the data processor circuit to 8-bit data and outputs the converted data. In this manner, a regular image is converted into an image similar to a draft-design image.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: April 10, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masato Teratani, Tomomichi Nakai
  • Patent number: 6768513
    Abstract: An image signal processor detects deficient pixels, such as pixels having a white deficiency or a black deficiency, and corrects the image signal so that the pixel deficiency is not reproduced. A memory circuit holds a target pixel signal and peripheral signals, which correspond to the pixels adjacent to the target pixel. A deficiency detection circuit compares the level of the target pixel signal with the levels of the peripheral pixel signals to detect whether the target pixel is deficient. A deficiency correction circuit corrects the signal of a detected deficient pixel using information from nearby pixels.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: July 27, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tohru Watanabe, Masato Teratani
  • Publication number: 20040091167
    Abstract: Image data of a target pixel and peripheral pixels are stored in a memory. Using a most significant bit extractor circuit, 4 most significant bits of data are extracted from each image data. A histogram circuit generates a histogram of the extracted 4-bit data. Referring to the histogram, a data processor circuit (17) replaces the image data of the target pixel with a maximum value of the numbers of pixels having the same level and outputs the processed data. Then, a digit-complementing circuit converts the data output from the data processor circuit to 8-bit data and outputs the converted data. In this manner, a regular image is converted into an image similar to a draft-design image.
    Type: Application
    Filed: September 4, 2003
    Publication date: May 13, 2004
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masato Teratani, Tomomichi Nakai
  • Publication number: 20040012696
    Abstract: A method for correcting a deficient image signal without lowering the resolution of a display page. The method includes generating an image signal of a subject pixel and image signals of peripheral pixels arranged about the subject pixel. A maximum level and a minimum level of the image signals of the peripheral pixels are detected. The method generates a first reference value by adding a first offset value to the maximum level and a second reference value by subtracting a second offset value from the minimum level. The method further includes generating a correction signal using at least one of the image signals of the peripheral pixels, and replacing the deficient image signal with the correction signal when the level of the image signal of the subject pixel is greater than the first reference value or less than the second reference value.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 22, 2004
    Inventors: Masato Teratani, Kazuhiro Kazui