Patents by Inventor Masato Tsunoda

Masato Tsunoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105422
    Abstract: A plasma processing apparatus includes: a processing container; a stage arranged inside the processing container to place a substrate to be processed on the stage; a plasma excitation antenna arranged above the processing container; a coil holder for holding the plasma excitation antenna; and a radio-frequency power supply for supplying radio-frequency power to the plasma excitation antenna. The coil holder includes a plurality of beam-like members arranged radially to protrude outward from a center of the coil holder, and a clamp-like member attached to each of the plurality of beam-like members and suspended downward from each of the plurality of beam-like members. The clamp-like member has an upper end supported by each beam-like member with a screw member and is configured to move in a pendulum manner, and a gripper configured to grip and hold the plasma excitation antenna is formed in a lower end of the clamp-like member.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 28, 2024
    Inventors: Masato OZAWA, Chanseong AHN, Masaki TSUNODA
  • Patent number: 7376928
    Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: May 20, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noriaki Matsuno, Masato Tsunoda, Hirofumi Wada
  • Publication number: 20070162884
    Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.
    Type: Application
    Filed: February 13, 2007
    Publication date: July 12, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Noriaki Matsuno, Masato Tsunoda, Hirofumi Wada
  • Patent number: 7194719
    Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: March 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noriaki Matsuno, Masato Tsunoda, Hirofumi Wada
  • Patent number: 6998654
    Abstract: A semiconductor integrated circuit device (10) is composed of an LSI function unit (11) and a shield wiring layer (22) formed on the unit. The LSI function unit (11) includes a semiconductor substrate (12) and a first insulating film (13), and the semiconductor substrate (12) is formed with a circuit element including, for example, a MOS transistor (14). The shield wiring layer (22) is composed of a lower shield line (23), a third insulating film (24), an upper shield line (25), and a fourth insulating film (26) sequentially stacked above a second insulating film (17). The directions in which the lower and upper shield lines (23) and (25) are arranged intersect each other.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: February 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Rie Itoh, Noriaki Matsuno, Masato Tsunoda
  • Publication number: 20050280038
    Abstract: A semiconductor integrated circuit device (10) is composed of an LSI function unit (11) and a shield wiring layer (22) formed on the unit. The LSI function unit (11) includes a semiconductor substrate (12) and a first insulating film (13), and the semiconductor substrate (12) is formed with a circuit element including, for example, a MOS transistor (14). The shield wiring layer (22) is composed of a lower shield line (23), a third insulating film (24), an upper shield line (25), and a fourth insulating film (26) sequentially stacked above a second insulating film (17). The directions in which the lower and upper shield lines (23) and (25) are arranged intersect each other.
    Type: Application
    Filed: July 14, 2003
    Publication date: December 22, 2005
    Inventors: Rie Itoh, Noriaki Matsuno, Masato Tsunoda
  • Publication number: 20050050507
    Abstract: A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the wires being on one of opposite sides, and the other ends of the wires being on the other one of the opposite sides, wherein: each of the one ends of the wires is point-symmetric to any of the other ends of the wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.
    Type: Application
    Filed: August 10, 2004
    Publication date: March 3, 2005
    Inventors: Noriaki Matsuno, Masato Tsunoda, Hirofumi Wada