Abstract: According to an embodiment, an acquisition circuit, a modification circuit, and a compressor are included. The modification circuit executes a modification process of modifying first consecutive grids, the number of which is smaller than a preset threshold value in a preset linear scanning direction, among first grids indicating that the obstacle is absent to the second grids. The compressor continuously scans the OGM undergoing the modification process in the scanning direction and encodes the grids in a scanning order.

Abstract: According to one embodiment, an image processing device includes a synthesis processing unit. The synthesis processing unit synthesizes a plurality of depth maps. A depth map is generated based on images that are mutually different in viewpoint. The plurality of depth maps are mutually different in focal length. The depth map includes distance data in a distance range set in accordance with the focal length.

Abstract: According to one embodiment, an image encoder configured to write coded image data in a memory includes an encoding module, a write address determining module, and a memory controller. The encoding module divides original image data including a plurality of pixels into a plurality of block lines, divides each block line into a plurality of sub-block lines, encodes the original image data in each sub-block line, and generates a plurality of coded sub-block lines. The write address determining module determines a write address of the memory in each coded sub-block line based on a number of the sub-block lines, an original image data size of the original image data, and image coding rate. The memory controller writes the coded sub-block line in the write address corresponding to the coded sub-block line.

Abstract: According to one embodiment, an image encoder configured to write coded image data in a memory includes an encoding module, a write address determining module, and a memory controller. The encoding module divides original image data including a plurality of pixels into a plurality of block lines, divides each block line into a plurality of sub-block lines, encodes the original image data in each sub-block line, and generates a plurality of coded sub-block lines. The write address determining module determines a write address of the memory in each coded sub-block line based on a number of the sub-block lines, an original image data size of the original image data, and image coding rate. The memory controller writes the coded sub-block line in the write address corresponding to the coded sub-block line.

Abstract: A multiprocessor system includes cache memories each of which is provided in correspondence with one of processor cores and includes a tag storage unit configured to store validity information representing whether a cache line as a unit to store data is valid, update information representing whether data in the cache line has been rewritten, and address information of the data in the cache line, a shared memory shared by the processor cores, and an arbitration circuit configured to arbitrate access requests from the processor cores to the shared memory and send the arbitrated access request to the cache memories. Each cache memory includes a violation detection circuit configured to detect a violation access by comparing the information in the tag storage unit with the access request from the arbitration circuit.

Abstract: In a compression/decompression apparatus that compresses or decompresses a plurality of sub-block data elements, a compressing unit compresses the plurality of sub-block data elements in parallel by a plurality of compressors. A combining unit combines compressed data by the plurality of compressors to generate a transfer data such that the transfer data has a transfer data amount corresponding to a plurality of transferring cycles, each transfer data amount per one transferring cycle is divided into a plurality of segmented regions in same number as number of the sub-block data elements, and allocating each compressed data of the plurality of sub-block data elements is allocated to a corresponding segmented region of the plurality of segmented regions, and outputs the transfer data to the external memory. A decompressing unit decompresses the transfer data read from the external memory in parallel by using a plurality of decompressors. An arranging unit performs address conversion.

Abstract: A general-purpose register file including a plurality of general-purpose registers stores parallel arithmetic data. A plurality of pattern registers store a plurality of items of pattern data indicating the rearrangement of data in bytes, in half words, in words, or in a combination of these units. A data select circuit selects one of the items of pattern data stored in the plurality of pattern registers according to specifying data included in an instruction. A rearranging circuit rearranges parallel arithmetic data according to the item of pattern data selected by the data select circuit.

Abstract: A data compression and decompression apparatus according to an embodiment of the present invention comprises: a plurality of compression modules that implements compression algorithms with the same compression rate and different throughputs, respectively, a plurality of decompression modules that implements decompression algorithms corresponding to the compression algorithms of the compression modules, respectively, and an algorithm switching unit that switches a compression module to be used for compression of the write data and a decompression module to be used for decompression of the compressed data according to a progress of data processing in the data processing module.

Abstract: A compression/decompression apparatus according to the present invention divides a transfer data amount per cycle, and after allocating compressed data in a predetermined amount of at least two sub-block data elements of a plurality of compressed sub-block data elements to each segmented region, combines elements of compressed data in respective segmented regions to generate transfer data, and the compression/decompression apparatus decompresses compressed data of read transfer data allocated to each segmented region in parallel and performs address conversion so that the compressed data is arranged at an original position in block data.

Abstract: A multiprocessor system includes cache systems arranged in correspondence with processor cores, and each including a cache memory which stores a cache line, a shared memory shared by the processor cores, and an arbiter configured to arbitrate access requests sent from the cache systems to the shared memory, and configured to send the arbitrated access request to the shared memory and the cache systems. The cache system includes a determination circuit configured to determine an access state using line information and the access request sent from the arbiter, a flag circuit configured to set a flag for each cache line based on a determination result of the determination circuit, and a control circuit configured to confirm the flag when a read access or a write access is made to a cache line held in the cache memory, and configured to detect a violation access based on the flag.

Abstract: A general-purpose register file including a plurality of general-purpose registers stores parallel arithmetic data. A plurality of pattern registers store a plurality of items of pattern data indicating the rearrangement of data in bytes, in half words, in words, or in a combination of these units. A data select circuit selects one of the items of pattern data stored in the plurality of pattern registers according to specifying data included in an instruction. A rearranging circuit rearranges parallel arithmetic data according to the item of pattern data selected by the data select circuit.

Abstract: A multiprocessor system includes cache memories each of which is provided in correspondence with one of processor cores and includes a tag storage unit configured to store validity information representing whether a cache line as a unit to store data is valid, update information representing whether data in the cache line has been rewritten, and address information of the data in the cache line, a shared memory shared by the processor cores, and an arbitration circuit configured to arbitrate access requests from the processor cores to the shared memory and send the arbitrated access request to the cache memories. Each cache memory includes a violation detection circuit configured to detect a violation access by comparing the information in the tag storage unit with the access request from the arbitration circuit.

Abstract: According to the present invention, there is provided an instruction cache prefetch control apparatus having an external memory, a CPU and an instruction cache unit, the instruction cache unit having: an instruction cache data memory which receives and stores the instruction sequence; a prefetch buffer which prefetches and stores an instruction sequence next to the instruction sequence as a target of a fetch request from the CPU when the next instruction sequence is not stored in the instruction cache data memory; an instruction cache write control unit which selectively outputs, to the instruction cache data memory, one of the instruction sequence output from the external memory and the instruction sequence stored in the prefetch buffer; and a hit or miss determination access control unit which, upon receiving, from the CPU, a fetch request for the instruction sequence stored in the prefetch buffer, transfers the instruction sequence from the prefetch buffer to the instruction cache data memory and stores th

Abstract: An apparatus for organizing a processor includes a execution cycle calculator calculating an execution cycle time of a pipeline processor, an access time calculator calculating a memory access time of an internal memory contained in the pipeline processor, and a configuration storage unit storing a memory access time of the internal memory reset in integer value times of the execution cycle time, when the memory access time is longer than the execution cycle time.

Abstract: A processor includes an instruction fetch unit providing a fetch address to the memory system; a branch buffer, a normal buffer, and a general buffer, which receive fetch instructions, respectively; a to-be-issued instruction selecting unit, which selects an instruction from the normal buffer, the branch buffer, and the general buffer and issues the instruction in conformity with an instruction from the instruction buffer control unit; an instruction decoding unit, which receives the instruction issued from the to-be-issued instruction selecting unit, decodes the issued instruction, and transmits decoded results to the instruction buffer control unit; a loop processing unit, which receives the decoded results from the instruction decoding unit and transmits a loop start address to the instruction fetch unit; and a branch determination unit, which transmits a fetch address to the instruction fetch unit established when a branching condition is satisfied or not satisfied.

Abstract: A branch predictor configured to communicate information between first and second thread execution units includes a first branch prediction table configured to store branch prediction information of the first thread execution unit. A second branch prediction table is configured to store branch prediction information of the second thread execution unit. A read address register is configured to access the first and second branch prediction tables based on a read address received from the first thread execution unit. A selector is configured to select one of the first and second branch prediction tables in accordance with the read address, to read the branch prediction information of one of the first and second thread execution units, and to supply read branch prediction information to the first thread execution unit when the second thread execution unit is in a wait state.

Abstract: An apparatus for organizing a processor includes a execution cycle calculator calculating an execution cycle time of a pipeline processor, an access time calculator calculating a memory access time of an internal memory contained in the pipeline processor, and a configuration storage unit storing a memory access time of the internal memory reset in integer value times of the execution cycle time, when the memory access time is longer than the execution cycle time.

Abstract: To improve the detection precision and detection efficiency and further to automatize the detection process, moisture in a honeycomb panel is detected as follows: the honeycomb panel is heated by a lamp; the surface temperature of the heated construction is measured by an infrared radiation thermometer; the measured temperature is displayed to roughly discriminate an abnormal portion (i.e., a portion containing moisture); the honeycomb panel is further heated continuously to detect temperature-change-rates at both abnormal and normal portions (i.e., a portion not containing moisture); and the two temperature-change-rates are compared with each other to discriminate a presence of moisture.