Patents by Inventor Masato Yokobayashi

Masato Yokobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8269353
    Abstract: Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: September 18, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Miyata, Hiroyuki Nakanishi, Masahiro Okita, Kazuaki Tatsumi, Masato Yokobayashi
  • Publication number: 20110064984
    Abstract: A solar battery module substrate includes an insulating substrate on which a conductive pattern and an insulating protective film are formed, the conductive pattern including: cathode mounting terminals each of which is to be connected with a cathode of a solar battery cell; anode mounting terminals each of which is to be connected with an anode of the solar battery cell; and first module wiring, the first module wiring connecting a cathode mounting terminal to be connected with a cathode of one solar battery cell with an anode mounting terminal to be connected with an anode of another solar battery cell connected in series with said one solar battery cell, the insulating protective film having at least one opening for exposing the cathode mounting terminal and the anode mounting terminal, and the opening being positioned inside a portion of the solar battery module substrate on which portion the solar battery cell is to be projected.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 17, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuaki TATSUMI, Kohji MIYATA, Hiroyuki NAKANISHI, Masahiro OKITA, Masato YOKOBAYASHI
  • Publication number: 20100313930
    Abstract: All solar battery cells are in a matrix disposition. Each row of the matrix includes at least two cell groups, and each column of the matrix includes at least two cell groups.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 16, 2010
    Inventors: Masato Yokobayashi, Tomotoshi Satoh, Hiroyuki Nakanishi
  • Publication number: 20100294342
    Abstract: A solar cell module 1 includes a plurality of solar cells 30. Each of the plurality of solar cells 30 is disposed on a corresponding one of a plurality of pad sections in such a manner that the each of the plurality of solar cells 30 is electrically connected to the corresponding one of the plurality of pad sections. The each of the plurality of solar cells 30 is electrically connected to a corresponding inner lead section 120. A cathode section 114 and an anode section 116 feed an electric current generated by the plurality of solar cells 30. A metal lead frame is provided such that the plurality of pad sections, the inner lead sections 120, the cathode section 114 and the anode section 116 are provided therein as a part of the lead frame itself. This configuration enables the solar cell module 1 to endure against bending stress and to be curved. As a result, it is possible to provide a solar cell module which can be disposed along a curved surface of an electronics device.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 25, 2010
    Inventors: Hiroyuki Nakanishi, Kohji Miyata, Yoshihide Iwazaki, Seiji Ishihara, Masato Yokobayashi, Etsuko Ishizuka, Kiyoharu Shimano, Katsunobu Mori
  • Publication number: 20100294358
    Abstract: A semiconductor chip and an interposer are bonded by a conductive die bonding material. Between the semiconductor chip and the interposer, an application region in which the die bonding material resides and a region in which a sealing resin resides are provided. This allows adhesivity between the semiconductor chip and the interposer to be higher than that in conventional semiconductor packages, thereby causing no detachment at the adhesive interface. As a result, it becomes possible to improve electrical property and long-term reliability as compared to conventional semiconductor packages. Moreover, it is also possible to prevent the semiconductor chip from warping.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 25, 2010
    Inventors: Hiroyuki NAKANISHI, Masahiro Okita, Kohji Miyata, Tomotoshi Satoh, Etsuko Ishizuka, Masato Yokobayashi
  • Publication number: 20100148311
    Abstract: Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 17, 2010
    Inventors: Koji MIYATA, Hiroyuki Nakanishi, Masahiro Okita, Kazuaki Tatsumi, Masato Yokobayashi
  • Publication number: 20080157359
    Abstract: An electronic component according to the present invention includes a land 112 having a flat reference surface p1 and having a solder joint p3 to be solder bonded, wherein the solder joint p3 as a concave 113 recessed from the reference surface, and a nickel plate layer 114 is laminated on a surface of the land 112, and a position of an interface between (a) a tin-containing alloy layer 116 formed on the solder joint p3 of the nickel plate layer 114 in solder bonding the nickel plate layer 114 and (b) the nickel plate layer 114 deviates from a plane including the reference surface p1. This makes it possible to provide an electronic component including a solder joint which hardly cracks.
    Type: Application
    Filed: December 18, 2007
    Publication date: July 3, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masato Yokobayashi, Katsuyuki Tarui