Abstract: A Content Addressable Memory (CAM) encoder comprises either a prefetch circuit or a flag data sense circuit. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and enables a large capacity CAM to operate at high speeds. Moreover, a semiconductor integrated circuit detects the differential current between the current flowing through a first signal line and the reference current flowing through a second signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock and operates as the timing control circuit to predict the termination of the encoding operation. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed.

Abstract: In an associative memory comprising a function to extend data width, for which match retrieval is to be conducted, up to a plurality of words, that is, a function to detect total match data when match is respectively detected for a plurality of continuous retrievals, power consumption can be reduced by making active only the necessary areas under the condition that the whole circuit is no longer required to be made active through execution of the current retrieval only to the blocks for which match is detected in the preceding retrieval during a plurality of continuous retrieving operations and/or its adjacent blocks.

Abstract: There are provided a data flow control apparatus for outputting data through a switchover and a memory apparatus in which such a data flow control apparatus is incorporated. A replacement data is defined for an array of addresses which would not appear sequentially as in a branch instruction and the like. The replacement data is only outputted when the address data are inputted in the order of the array. Thus, it is possible to prevent an illegal copy of softwares.

Abstract: An associative memory device is cascade-connected to form an associative memory. The associative memory device includes a retrieval result register for storing a retrieval result of the lo associative memory device and the retrieval result of the associative memory devices of an upstream side of the associative memory device. An identification code register stores an identification code that indicates whether the associative memory device is a last stage associative memory device of the cascade-connected associative memory devices. If the associative memory device is the last stage associative memory device, the retrieval result stored in the retrieval result register is output. The associative memory outputs the retrieval result only when a signal instructing an output of the retrieval result is received.

Abstract: A priority encoder is provided with priority circuitry for sequentially producing priority-ordered output signals and encoding circuitry for encoding the output signal. Small input, small unit priority circuits are used to form the priority circuitry into a hierarchical structure. An OR output of a small unit priority circuit in a lower hierarchy is used as an input signal of another small unit priority circuit in a higher hierarchy. An output signal of the priority circuit in the higher hierarchy has an address which corresponds to the address of the one input signal and is made an enable signal of the priority circuit in the lower hierarchy. The priority encoder, though simple in structure and formed with a small number of elements, operates at a high speed. Moreover, an encoder with a prefetch circuit is built into the priority encoder provided for a CAM block.

Abstract: A pair of attribute and data is stored in each word memory of associative memories. A retrieval is performed using reference data applied from an exterior and the pair of attribute and data stored in each word memory of associative memories. Upon receipt of a match of the attribute, a signal representing a match or mismatch of both attribute and data except the attribute is supplied to a data line. At the time of subsequent retrieval, upon receipt of a match of the attribute, data appearing on the data line is taken in.

Abstract: A pair of attribute and data is stored in each word memory of associative memories. A retrieval is performed using reference data applied from an exterior and the pair of attribute and data stored in each word memory of associative memories. Upon receipt of a match of the attribute, a signal representing a match or mismatch of both attribute and data except the attribute is supplied to a data line. At the time of subsequent retrieval, upon receipt of a match of the attribute, data appearing on the data line is taken in.

Abstract: There is disclosed an associative memory capable of reducing electricity to be consumed. Prior to a retrieval, a number of match lines, which associate with a number of word memories, respectively, are precharged. In the retrieval, among the multiple match lines which are subjected to the precharge, the match line associated with the word memory which stores a bit pattern equivalent to that for the retrieval is discharged.

Abstract: In a semiconductor memory comprising first bit lines, second bit lines and first nonvolatile split gate memory cells and second nonvolatile split gate memory cells respectively having common source electrodes, memory gate electrodes connected to common memory gate lines, and drain electrodes connected, respectively, to the first bit lines and the second bit lines, a source voltage applying means applies a voltage VS different from a voltage applied to the substrate and meeting a relation represented by:min(VB1, VB2)<VS<max(VB1, VB2)where VB1 is a voltage of the first bit line, VB2 is a voltage applied to the second bit line, min(VB1, VB2) is the lower one of the voltages VB1 and VB2, and max(VB1, VB2) is the higher one of the voltages VB1 and VB2, to the source electrode in writing data on the first nonvolatile split gate memory cell.

Abstract: The address gate electrode of two nonvolatile split gate memory cells are arranged horizontally on the opposite sides of a bit line. The address gate electrode of the first memory cell is nearer to the bit line than the memory gate electrode of the same nonvolatile split gate memory cell. The memory gate electrode of the second nonvolatile split gate memory cell is nearer to the bit line than the address gate electrode of the second nonvolatile split gate memory cell.

Abstract: A semiconductor integrated circuit is a CAM memory which comprises at least one memory cell including a first storage unit for defining the electrical connection and otherwise the non-connection between a first data line and a match line and a second storage unit for defining the electrical non-connection and otherwise the connection between a second data line and the match line, and a control word line for controlling said first and second storage units in the memory cell, the match line corresponding to at least one of the control word lines, the control word line being used to effect the connection and otherwise non-connection between each of said first and second data lines and the match line in accordance with the definition of connections of said first and second storage units.

Abstract: A semiconductor integrated circuit capable of retrieving data from a number of memory cells without mutual interference at high speed and making it possible to build a large capacity data base at higher speed is provided with a set of retrieval memory word blocks including a first and a second memory unit respectively for defining the electrical connection or otherwise nonconnection between a first or second data line and a source electrode line and a control word line for controlling these memory units, a match line having a first potential setting means for setting a first potential beforehand, a sense amplifier for detecting the potential of the match line, and a second potential fixing means for fixing the potential of the match line to a second potential with the source electrode line as a control input.

Abstract: A semiconductor integrated circuit has a CAM structure based on nonvolatile memories which is used for forming a flexible CAM of large scale integration. The circuit includes a first memory cell for defining the electrical connection or the nonconnection between a first data line and a match line, a second memory cell for defining the electrical nonconnection or the connection between a second data line and the match line, and a selective transistor for making or breaking the connection between each of the first and the second data lines and the match line. The threshold voltage of the selective transistor has a predetermined value incorporated during the fabrication process. The semiconductor integrated circuit can electrically connect a selective word line connected to a gate electrode of the selective transistor to the match line and has a tri-state buffer for making the potential of the selective word line float. The threshold voltage of each nonvolatile memory is set at a predetermined voltage.

Abstract: In selectors 21.sub.0 -21.sub.3 two pull-up switching elements 40-40.sub.3, 42.sub.0 -42.sub.3, the elements being connected in series to each other in each selector, are additionally provided instead of a don't care-setting two-input NAND gate, for connecting or disconnecting connection lines of outputs of positive logic switching elements 24.sub.0 -24.sub.3 and those of negative logic switching elements 23.sub.0 -23.sub.3 with or from a power supply line Vdd. First memory cells M.sub.00 -M.sub.30 control on-off states of negative logic switching elements 23.sub.0 -23.sub.3 and ones 40.sub.0 -40.sub.3 of pull-up switching elements, and second memory cells M.sub.01 -M.sub.31 control on-off states of positive logic switching elements 24.sub.0 -24.sub.3 and the others 42.sub.1 -42.sub.3 of the pull-up switching elements. Thus, use of a prior art two-input NAND gate is eliminated and hence the number of transistors is reduced.

Abstract: In a semiconductor integrated circuit, upstream slave mode logic devices are informed successively of the completion of configuration for each slave mode logic device through a data line connected to the slave side, and a master mode logic device is finally informed of the completion of the configuration for all slave mode logic devices. Hereby, generation of a basic clock for the master mode logic device is controlled without use of a large-scaled circuit such as a pulse counter. Additionally, period of the clock supplied from said master mode logic device to each slave mode logic device is temporarily changed upon the completion of the configuration for all slave mode logic devices to inform each slave mode logic device of the completion of the configuration of all slave mode logic devices.