Abstract: In order to lay out a driver circuit having high drivability without increasing a semiconductor chip area, a macro cell (22) such as a clock driver having a large fan-out is arranged under a feeder line (20). It is possible to feed the macro cell (22) from the feeder line (20), which is a second layer aluminum wire, in a short distance. An input signal line (23) and an output signal line (24) which are connected to input and output pins of the macro cell (22) are provided in positions not to be in contact with the feeder line (20). Since the macro cell (22) is arranged in a portion of an internal region which is located under the feeder line (20), it is possible to suppress increase of the layout area as well as electromigration caused by feeding to the macro cell (22).

Abstract: It is an object of the present invention to design in a short period of time a semiconductor integrated circuit device capable of stable operation with high noise margin by reducing effects of noise caused by coupling capacitance between clock signal lines and other signal lines in a semiconductor integrated circuit device with a finer structure. A macro-cell (1a) used in designing with a Computer Aided Design system has a structure in which a clock signal line (6) is interposed and shielded between V.sub.DD power-supply lines (4 and 4a). By using such a basic macro-cell (1a) with the shielded clock signal line (6), coupling capacitance can always be reduced between the clock signal lines and other signal lines formed in interconnection spaces even when using the Computer Aided Design.

Abstract: A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.

Abstract: In order to lay out a driver circuit having high drivability without increasing a semiconductor chip area, a macro cell (22) such as a clock driver having a large fan-out is arranged under a feeder line (20). It is possible to feed the macro cell (22) from the feeder line (20), which is a second layer aluminum wire, in a short distance. An input signal line (23) and an output signal line (24) which are connected to input and output pins of the macro cell (22) are provided in positions not to be in contact with the feeder line (20). Since the macro cell (22) is arranged in a portion of an internal region which is located under the feeder line (20), it is possible to suppress increase of the layout area as well as electromigration caused by feeding to the macro cell (22).

Abstract: A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.

Abstract: A semiconductor integrated circuit device with an ECL sequential circuit is disclosed, which comprises a data holding circuit provided the ECL sequential circuit for holding the output thereof, and an emitter follower for feeding the output of the data holding circuit as an input thereof, and an emitter follower circuit control circuit thereto. The emitter follower current when the emitter potential on the emitter follower is at a high level, is set to be lower than the emitter follower current when the emitter potential is at a low level.