Abstract: A semiconductor integrated circuit includes an oscillation circuit and first and second current control circuits. The oscillation circuit includes a first series circuit having inverters, including a first inverter, connected in series and a second series circuit having inverters, including a second inverter, connected in series. An oscillation signal is output from the first series circuit. The first current control circuit is connected between a current source and an output terminal of the first inverter and configured to control a current from the current source into the first series circuit in accordance with a first signal synchronized with a clock signal. The second current control circuit is connected between an output terminal of the second inverter and a reference voltage node and configured to control a current from the second series circuit to the reference voltage node in accordance with a second signal synchronized with the clock signal.

Abstract: A semiconductor device has a current controlled oscillation circuit configured to generate an oscillation clock in response to a current supplied, a first circuit configured to output a first signal when a phase of the oscillation clock is later than a phase of reception data, and to output a second signal when a phase of the oscillation clock is earlier than a phase of the reception data, and a current control circuit configured to control a current to be supplied to the current controlled oscillation circuit such that the number of times of output of the first signal from the first circuit matches the number of times of output of the second signal from the first circuit.

Abstract: A semiconductor integrated circuit includes an oscillation circuit and first and second current control circuits. The oscillation circuit includes a first series circuit having inverters, including a first inverter, connected in series and a second series circuit having inverters, including a second inverter, connected in series. An oscillation signal is output from the first series circuit. The first current control circuit is connected between a current source and an output terminal of the first inverter and configured to control a current from the current source into the first series circuit in accordance with a first signal synchronized with a clock signal. The second current control circuit is connected between an output terminal of the second inverter and a reference voltage node and configured to control a current from the second series circuit to the reference voltage node in accordance with a second signal synchronized with the clock signal.

Abstract: A semiconductor device has a current controlled oscillation circuit configured to generate an oscillation clock in response to a current supplied, a first circuit configured to output a first signal when a phase of the oscillation clock is later than a phase of reception data, and to output a second signal when a phase of the oscillation clock is earlier than a phase of the reception data, and a current control circuit configured to control a current to be supplied to the current controlled oscillation circuit such that the number of times of output of the first signal from the first circuit matches the number of times of output of the second signal from the first circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit device comprises first and second transistors having control terminals receiving an input signal and an inversion signal of the input signal, third and fourth transistors having control terminals receiving the input signal and the inversion signal, first and second inverters in which outputs are connected to inputs of other converters, and a fifth transistor connected to the first to fourth transistors. The third and fourth transistors are connected to outputs of the second and the first inverters. Clock signal is supplied to the fifth transistor.

Abstract: A receiving device includes a phase-locked loop (PLL) circuit having a current control oscillator, a phase detector, an integral path, and a proportional path. The current control oscillator can generate an oscillation clock based on a first and second current. The phase detector can acquire a phase detection result based on the oscillation clock and a received signal. The integral path can generate the first current based on an integrated value of the phase detection results and supply the first current to the current control oscillator. The proportional path includes a digital-to-current converter to generate the second current based on the phase detection result and supply the second current to the current control oscillator. The receiving device includes a controller configured to adjust the second current based on frequency-current characteristics of the current control oscillator.

Abstract: According to one embodiment, a semiconductor integrated circuit device comprises first and second transistors having control terminals receiving an input signal and an inversion signal of the input signal, third and fourth transistors having control terminals receiving the input signal and the inversion signal, first and second inverters in which outputs are connected to inputs of other converters, and a fifth transistor connected to the first to fourth transistors. The third and fourth transistors are connected to outputs of the second and the first inverters. Clock signal is supplied to the fifth transistor.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a variable delay circuit is electrically connected to the correction circuit and configured to change a delay amount of the second clock. An adjustment circuit is electrically connected to a summer circuit. The adjustment circuit is configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a variable delay circuit is electrically connected to the correction circuit and configured to change a delay amount of the second clock. An adjustment circuit is electrically connected to a summer circuit. The adjustment circuit is configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results.

Abstract: A semiconductor circuit includes a plurality of transmitting circuits, each of which receives a corresponding one of synchronized first clock signals input thereto and includes a first circuit outputting a third clock signal which is generated by dividing the frequency of an unsynchronized second clock signal and is synchronized with the first clock signal, a phase comparator comparing phases of the first clock signal and the third clock signal, and a reset signal generator setting, if a phase shift is detected by the phase comparator, the first signal at a first logic level for a predetermined period. The first circuit enters a reset state during a period in which the first signal is at the first logic level, and, when the first signal changes from the first logic level to a second logic level, is released from a reset state and generates the third clock signal synchronized with the first clock signal.

Abstract: A semiconductor circuit includes a plurality of transmitting circuits, each of which receives a corresponding one of synchronized first clock signals input thereto and includes a first circuit outputting a third clock signal which is generated by dividing the frequency of an unsynchronized second clock signal and is synchronized with the first clock signal, a phase comparator comparing phases of the first clock signal and the third clock signal, and a reset signal generator setting, if a phase shift is detected by the phase comparator, the first signal at a first logic level for a predetermined period. The first circuit enters a reset state during a period in which the first signal is at the first logic level, and, when the first signal changes from the first logic level to a second logic level, is released from a reset state and generates the third clock signal synchronized with the first clock signal.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second power source in the each standard cell, wherein the first diffusion layers as well as the second diffusion layers of neighboring standard cells are integrally formed.

Abstract: Disclosed is a serial-to-parallel converter/parallel-to-serial converter/FIFO unified circuit which includes a register, a selector and a counter. The register receives serial input data and converts the serial data into parallel data based on frequency-divided multi-phase clock signals from a counter. The selector receives the parallel data from the register to select one of the data in accordance with a control signal. The counter generates the control signal for the selector so that plural items of data will be output serially from the selector in the sequence in which the plural items data have been serially supplied to the register.

Abstract: A latch circuit includes: a first terminal; a second terminal; a first data-gating circuit coupled to the first terminal and the second terminal, the first data-gating circuit non-reversely gating the second signal in response to the first signal to reveal a third signal; a second data-gating circuit coupled to the first terminal and the second terminal, the second data-gating circuit reversely gating the second signal in response to the first signal to reveal a fourth signal; a third terminal receiving a fifth signal; a selector circuit coupled to the first data-gating circuit and the second data-gating circuit, the selector circuit outputting one of the third signal and the fourth signal in response to the fifth signal to latch one of the third signal and the fourth signal, respectively; and a bistable circuit coupled to the selector circuit, the bistable circuit holding one of the third signal and the fourth signal.

Abstract: A differential output circuit includes a bias circuit connected with a first voltage. An input circuit section includes first and second MOS transistors of a first conductive type, and the first and second MOS transistors are connected with the first voltage through the bias circuit, and gates of the first and second MOS transistors receive a differential input signal. Third and fourth MOS transistors of a second conductive type are connected with the first and second MOS transistors through first and second resistance elements, respectively, and connected with a second voltage. A first connection node between the first MOS transistor and the first resistance element is connected with a gate of the fourth MOS transistor, and a second connection node between the second MOS transistor and the second resistance element is connected with a gate of the third MOS transistor.