Abstract: A compiler program causes a computer to execute optimization processing for an optimization target program. The optimization target program includes a loop including a vector store instruction and a vector load instruction for an array variable. The optimization processing includes (1) unrolling the vector store instruction and the vector load instruction in the loop by an unrolling number of times to generate a plurality of unrolled vector store instructions and a plurality of unrolled vector load instructions, and (2) scheduling to move an unrolled vector load instruction among the plurality of unrolled vector load instructions, which is located after a first unrolled vector store instruction that is located at first among the plurality of unrolled vector load instructions, before the first unrolled vector store instruction.

Abstract: A compiler program causes a computer to execute optimization processing for an optimization target program. The optimization target program includes a loop including a vector store instruction and a vector load instruction for an array variable. The optimization processing includes (1) unrolling the vector store instruction and the vector load instruction in the loop by an unrolling number of times to generate a plurality of unrolled vector store instructions and a plurality of unrolled vector load instructions, and (2) scheduling to move an unrolled vector load instruction among the plurality of unrolled vector load instructions, which is located after a first unrolled vector store instruction that is located at first among the plurality of unrolled vector load instructions, before the first unrolled vector store instruction.

Abstract: A method of compiling a first program to output a second program, the method includes: determining a number of arithmetic units to be operated during execution of the second program for each of a plurality of sections in the first program; and creating the second program by adding an instruction to specify the number of arithmetic units to be operated to each of the plurality of sections based on the determining.

Abstract: A processor includes an instruction executing unit which executes a memory access instruction, a cache memory unit disposed between a main memory which stores data related to the memory access instruction and the instruction executing unit, a control information retaining unit which retains control information related to a prefetch issued to the cache memory unit, an address information retaining unit which retains address information based on the memory access instruction executed in the past, and a control unit which generates and issues a hardware prefetch request. The control unit compares address information retained in the address information retaining unit and an access address in the memory access instruction executed, and generates and issues based on a comparison result a hardware prefetch request to the cache memory unit according to the control information of the control information retaining unit specified by specifying information added to the memory access instruction.

Abstract: A processor includes an instruction executing unit, which executes a memory access instruction, a cache memory unit, disposed between a main memory which stores data related, to the memory access instruction and the instruction executing unit, a control information retaining unit which retains control information related to a prefetch issued to the cache memory unit, an address information retaining unit which retains address information based on the memory access instruction executed in the past, and a control unit which generates and issues a hardware prefetch request. The control unit compares address information retained in the address information retaining unit and an access address in the memory access instruction executed, and generates and issues based on a comparison result a hardware prefetch request to the cache memory unit according to the control information of the control information retaining unit, specified by specifying information added to the memory access instruction.

Abstract: A method of compiling a first program to output a second program, the method includes: determining a number of arithmetic units to be operated during execution of the second program for each of a plurality of sections in the first program; and creating the second program by adding an instruction to specify the number of arithmetic units to be operated to each of the plurality of sections based on the determining.

Abstract: In a compiler apparatus, a memory unit stores a first code including a loop having a first arithmetic expression including a first variable that refers to a result of K iterations previous calculation. A transformation unit develops the first arithmetic expression into a second arithmetic expression not including the first variable, using a second variable that refers to a result of K+1 iterations or more previous calculation, compares an execution time for executing the loop on the basis of the first arithmetic expression with an execution time for executing the loop in which the calculations of Jth and J+Kth iterations of the loop are executed in parallel on the basis of the second arithmetic expression, and decides based on the comparison result whether to transform the first code into a second code including a parallel processing instruction for executing the Jth and J+Kth iterations in parallel.

Abstract: In a compiler apparatus, a memory unit stores a first code including a loop having a first arithmetic expression including a first variable that refers to a result of K iterations previous calculation. A transformation unit develops the first arithmetic expression into a second arithmetic expression not including the first variable, using a second variable that refers to a result of K+1 iterations or more previous calculation, compares an execution time for executing the loop on the basis of the first arithmetic expression with an execution time for executing the loop in which the calculations of Jth and J+Kth iterations of the loop are executed in parallel on the basis of the second arithmetic expression, and decides based on the comparison result whether to transform the first code into a second code including a parallel processing instruction for executing the Jth and J+Kth iterations in parallel.

Abstract: An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address information based on a result of comparison processing between an address requested by a hardware prefetch request issuing section for memory access and address information held in an address information holding section, wherein when the control section causes the address information holding section to hold address information or address information in the address information holding section is updated, overwrite processing on the address information is inhibited for a predetermined time.

Abstract: In a computer where a software development tool program is started, an updating elapse degree and an execution frequency for a series of source programs used for generating an execution module are acquired. An optimization option of the level according to the updating elapse degree or the execution frequency is set for each of the source programs. Compiling accompanied by the optimization of the level indicated by the optimization option is performed for each of the source programs. Object programs created by the compiling are coupled.

Abstract: An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address information based on a result of comparison processing between an address requested by a hardware prefetch request issuing section for memory access and address information held in an address information holding section, wherein when the control section causes the address information holding section to hold address information or address information in the address information holding section is updated, overwrite processing on the address information is inhibited for a predetermined time.

Abstract: A compiler of this invention generates an object program 20 in which an area allocation instruction 11 to allocate an area for a structure of a list vector to be accessed in a loop and an area deallocation instruction 12 are converted into a new area allocation instruction 21 and a new area deallocation instruction 22, respectively. A new area allocation instruction processing unit 31 called by the new area allocation instruction 21 allocates an area 51 allocated in one operation of a size which is not less than an integral multiple of the size of an area for a structure, clips an area from the area 51, and assigns the area to the structure on a first area allocation request. The new area allocation instruction processing unit 31 clips an area contiguous to that for a previous structure from the area 51 allocated in one operation and assigns the area to a structure on second and subsequent calls.

Abstract: An apparatus for facilitating optimization processing in a compiler includes a language-specific-rule table which stores one or more predetermined rules which are specified for one or more programming languages; an analyzing unit which analyzes a program code which includes one or more instructions, and is described in one of the one or more programming languages, based on the one or more predetermined rules, to obtain an analysis result; and an embedding unit which embeds the analysis result in the program code.

Abstract: In a computer where a software development tool program is started, an updating elapse degree and an execution frequency for a series of source programs used for generating an execution module are acquired. An optimization option of the level according to the updating elapse degree or the execution frequency is set for each of the source programs. Compiling accompanied by the optimization of the level indicated by the optimization option is performed for each of the source programs. Object programs created by the compiling are coupled.

Abstract: In a multi-computer system having a plurality of computers, an input/output device configuration definition table and an input/output device configuration reference table are adapted to be collectively managed. A configuration management program manages the configuration definition of all input/output devices of a plurality of computers by using the input/output device configuration definition table, and generates a changed data file when an input/output device configuration is changed. Dynamic system alteration is effected by changing the contents of the input/output device configuration reference table stored in a shared memory, in accordance with the changed data file. The input/output device configuration definition table and the input/output device configuration reference table each have an input/output device information part and an input/output device connection information part arranged in a matrix form to allow addition/deletion of an input/output device and a computer.

Abstract: In a multi-computer system having a plurality of computers, an input/output device configuration definition table and an input/output device configuration reference table are adapted to be collectively managed. A configuration management program manages the configuration definition of all input/output devices of a plurality of computers by using the input/output device configuration definition table, and generates a changed data file when an input/output device configuration is changed. Dynamic system alteration is effected by changing the contents of the input/output device configuration reference table stored in a shared memory, in accordance with the changed data file. The input/output device configuration definition table and the input/output device configuration reference table each have an input/output device information part and an input/output device connection information part arranged in a matrix form to allow addition/deletion of an input/output device and a computer.

Abstract: In a multi-computer system having a plurality of computers, an input/output device configuration definition table and an input/output device configuration reference table are adapted to be collectively managed. A configuration management program manages the configuration definition of all input/output devices of a plurality of computers by using the input/output device configuration definition table, and generates a changed data file when an input/output device configuration is changed. Dynamic system alteration is effected by changing the contents of the input/output device configuration reference table stored in a shared memory, in accordance with the changed data file. The input/output device configuration definition table and the input/output device configuration reference table each have an input/output device information part and an input/output device connection information part arranged in a matrix form to allow addition/deletion of an input/output device and a computer.

Abstract: In a multi-computer system having a plurality of computers, an input/output device configuration definition table and an input/output device configuration reference table are adapted to be collectively managed. A configuration management program manages the configuration definition of all input/output devices of a plurality of computers by using the input/output device configuration definition table, and generates a changed data file when an input/output device configuration is changed. Dynamic system alteration is effected by changing the contents of the input/output device configuration reference table stored in a shared memory, in accordance with the changed data file. The input/output device configuration definition table and the input/output device configuration reference table each have an input/output device information part and an input/output device connection information part arranged in a matrix form to allow addition/deletion of an input/output device and a computer.

Abstract: In a multi-computer system having a plurality of computers, an input/output device configuration definition table and an input/output device configuration reference table are adapted to be collectively managed. A configuration management program manages the configuration definition of all input/output devices of a plurality of computers by using the input/output device configuration definition table, and generates a changed data file when an input/output device configuration is changed. Dynamic system alteration is effected by changing the contents of the input/output device configuration reference table stored in a shared memory, in accordance with the changed data file. The input/output device configuration definition table and the input/output device configuration reference table each have an input/output device information part and an input/output device connection information part arranged in a matrix form to allow addition/deletion of an input/output device and a computer.

Abstract: In a multi-computer system having a plurality of computers, an input/output device configuration definition table and an input/output device configuration reference table are adapted to be collectively managed. A configuration management program manages the configuration definition of all input/output devices of a plurality of computers by using the input/output device configuration definition table, and generates a changed data file when an input/output device configuration is changed. Dynamic system alteration is effected by changing the contents of the input/output device configuration reference table stored in a shared memory, in accordance with the changed data file. The input/output device configuration definition table and the input/output device configuration reference table each have an input/output device information part and an input/output device connection information part arranged in a matrix form to allow addition/deletion of an input/output device and a computer.