Abstract: A clock control unit (7) detects completion of data processing based on a busy signal BSY1 output by a geometry processing unit (4) and a busy signal BSY2 output by a rendering processing unit (5). The clock control unit (7) controls supply of a clock signal CLK1 to the geometry processing unit (4) and supply of a clock signal CLK2 to the rendering processing unit (5) so as to cause the geometry processing unit (4) and the rendering processing unit (5) to alternately operate.

Abstract: A clock control unit (7) detects completion of data processing based on a busy signal BSY1 output by a geometry processing unit (4) and a busy signal BSY2 output by a rendering processing unit (5). The clock control unit (7) controls supply of a clock signal CLK1 to the geometry processing unit (4) and supply of a clock signal CLK2 to the rendering processing unit (5) so as to cause the geometry processing unit (4) and the rendering processing unit (5) to alternately operate.

Abstract: An anti-alias font generator includes a stipple buffer that holds the gradation data of an anti-alias font, a source color register that sets a font display color, and a blender that blends the value of the source color register and the destination color value on the frame memory in accordance with the blend coefficient with the gradation data as the blend coefficient.

Abstract: Conventional systems mainly include technical aspects and it is not a main purpose to display a changed result accurately. Therefore, its processing time is significantly long.

Abstract: The apparatus comprises an input memory 102 for storing data necessary for geometrical operations, such as coordinate transformation, luminance calculation, and clipping operation of graphics; a global bus connected to the input memory; a plurality of floating process memories connected to the global bus, for receiving data necessary for geometrical operations; a sequencer for transmitting data necessary for geometrical operations, stored in the input memory, to the plurality of floating process memories; and a plurality of floating processing units each connected to a respective one of the plurality of floating process memories, for independently executing geometrical operations, using data transmitted from the floating process memories.

Abstract: Volume rendering apparatus including a voxel memory, a parameter provider, an address generator, a mapping unit, an image memory and a blender. The voxel memory stores original volume data. A parameter provider calculates a parameter of a volume plane which slices the volume object orthogonally to a direction of view, calculates a parameter of a three-dimensional mapping plane which slices the mapping object according to a point of view coordinate system and converts the three-dimensional mapping plane to a two-dimensional mapping plane. An address generator generates voxel memory addresses and image memory addresses and a mapping unit maps the volume plane on each of the mapping planes. An image memory stores mapping data and rendering data and a blender performs blending of data in the image memory and data on each of the mapping planes and writes the blended data back in the image memory.

Abstract: A graphic display unit makes it possible for a stereo display or blink operation to be implemented on a window system with each window having an arbitrary contour, and on a window by window basis. The graphic display unit of this invention comprises a frame buffer for a right eye, a frame buffer for a left eye, a window-id buffer which stores a window-id corresponding to the contour and position of windows on the frame buffer, a look-up table which stores control information related to stereo display and is accessed based on a window-id, a frame counter that issues the timing of switching frame buffers, a stereo display control circuit for switching buffers based on signals from both the look-up table and from the frame counter, and stereo viewer that controls shutters for a right eye and a left eye.

Abstract: A large screen display apparatus comprises a plurality of displays constituting a single large screen for displaying an object. The object is formed on the basis of screen data which is generated by a screen data generating section. Each of the displays is provided with a local data generating section for converting a coordinate of the screen data from the screen data generating section into a coordinate of a local coordinate system peculiar to the individual displays. Because the local data generating sections, each provided to one respective display, executes coordinate conversion to the screen data, it is possible to reduce load to the screen data generating section, and to thereby provide a display performance with a rapid response.

Abstract: This invention provides a circuit, which performs a high quality mapping operation by giving a perspective transformation effect to a mapping data of a rendering polygon. The circuit has a mechanism to divide edges and mapping data of a figure in a display and calculate a virtual mapping address, a pixel generator to generate a pixel data for pixels inside of the displayed figure and a virtual mapping address of the pixel data, a virtual address converter to convert the virtual mapping address to a mapping address, and a mapping memory to store the mapping data.

Abstract: By performing rotation and translation operations, a radar display converts a radar signal to radar image information expressed in a three-dimensional orthogonal coordinate system with horizontal, vertical, and depth coordinates related to a certain viewpoint. Terrain and target information is converted to the same coordinate system and combined with the radar image information, producing a realistic three-dimensional display. Clipping is performed in the depth direction to eliminate portions of the radar image disposed behind terrain or target images. Terrain and target images disposed behind the radar image are reduced in intensity, but not clipped. Perspective projection and zoom transformations may also be carried out.

Abstract: A straight line generator for line drawing in a discrete coordinate system utilizing the Bresenham algorithm. A first counter holds an X coordinate value and is capable of incrementing and decrementing the X coordinate value and a second counter holds a Y coordinate value and is capable of incrementing and decrementing the Y coordinate value. A region code which depends on the slope of the line within the range of 360 degrees is stored. An error term obtained from the Bresenham algirithm is also stored. Responsive to the region code and the error term, increments of the first and second counters are controlled. Positive and negative added parameters which vary the error are stored in registers. Either of the date in the register is selected in accordance with the sign of the error term so as to be added to the error term.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.

Abstract: A system for rotating an image by an arbitrary angle which is effective in image processing techniques using terminal equipment such as a work station, and will not distort a rotated image even with an increasing rotation angle .theta.. Skew transformation is implemented for respective skew angles in horizontal and vertical directions corresponding to a desired rotation angle three times alternately, so that affine transformation for image rotation may be replaced by triple skew transformations. Thus, arbitrary two-dimensional image data is precisely rotated by any desired angle at high speeds without resorting to approximation of the arithmetic equation.

Abstract: A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.