Patents by Inventor Masatoshi Kimura

Masatoshi Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210096849
    Abstract: An information processing apparatus includes a controller. A peripheral includes a converter and a device. The converter performs conversion of communication interface for inputs into the device based on a mode setting. When updating the embedded software of the device, the controller sets the converter to conversion mode to have the converter execute conversion of embedded software outputted using a first communication interface from the first communication interface to the second communication interface, and performs updating of the embedded software using the second communication interface. When not updating the embedded software, the controller sets the converter in non-conversion mode, stops the conversion from the first communication interface to the second communication interface, and stops the updating of the embedded software.
    Type: Application
    Filed: July 23, 2020
    Publication date: April 1, 2021
    Inventors: Akira TAKEUCHI, Masatoshi KIMURA, Hiroki TERAMOTO
  • Patent number: 10942793
    Abstract: An information processing system includes: a plurality of information processing devices each including a processor; and a relay device that connects the information processing devices via an expansion bus and relays communication between the information processing devices. The relay device includes a control unit that represents, for one of the information processing devices, the rest of the information processing devices, and communicates with the one of the information processing devices as an integrated information processing device of the relay device and the rest of the information processing devices.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 9, 2021
    Assignee: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Masatoshi Kimura, Tomohiro Ishida
  • Publication number: 20210064108
    Abstract: An information processing system includes a first information processing device, second information processing devices, and a relay device. The second information processing devices each include a second connector connected to the relay device, and a first restarter that restarts the second information processing devices. The relay device communicably connects the first and second information processing devices and includes a power supply control unit for power supply to the first and second information processing devices during restart of the relay device, and a second restarter that restarts the relay device in response to detection of a communication failure. The first information processing device includes a hot pluggable, first connector connected to the relay device, a first detector that detects restart of the relay device, and an initializer that initializes settings relating to communications via the relay device in response to detection of the relay device by the first detector.
    Type: Application
    Filed: July 27, 2020
    Publication date: March 4, 2021
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Masatoshi Kimura, Tomohiro Ishida, Yuki Kawama
  • Publication number: 20210042128
    Abstract: An information processing system includes information processors and a relay device. Each of the information processors includes a first communication device to transmit a reset signal representing initialization and to transmit/receive data. The relay device includes an input device and a hardware processor. The input device receives the reset signal from each of the information processors with bypassing second communication devices of the relay device. When the input device receives the reset signal, the hardware processor executes initialization processing of initializing one of the second communication devices that corresponds to one of the information processors serving as a transmission source of the data. The initialization processing is executed on a condition that one of the information processors, from which the reset signal has been transmitted, receives the data via a connection device.
    Type: Application
    Filed: June 4, 2020
    Publication date: February 11, 2021
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Tomohiro Ishida, Masatoshi Kimura, Yuji Nakayama
  • Publication number: 20200387468
    Abstract: An information processing system includes an information processing device, a computational processing device group, and a relay device. The information processing device corresponds to a host in the system. The computational processing device group includes a plurality of computational processing devices and corresponds to input/output (I/O) devices. The relay device has an expansion bus to which the information processing device and the computational processing device group are capable of connecting. The information processing device transmits data via the relay device to the computational processing device group. The computational processing device group executes distributed processing between the computational processing devices based on the data and transmits an execution result via the relay device to the information processing device.
    Type: Application
    Filed: April 29, 2020
    Publication date: December 10, 2020
    Inventors: Masatoshi KIMURA, Tomohiro ISHIDA
  • Publication number: 20200374977
    Abstract: An information processing system includes: a first relay device provided with a plurality of end points and a root complex for relay; and a second relay device provided with a plurality of end points and an end point for relay. The plurality of end points of the first relay device individually connects to any of a plurality of first information processing devices over an expansion bus. The root complex for relay: relays communication between the first information processing devices via the corresponding end points of the first relay device; connects to the second relay device over an expansion bus; and functions as a root complex. The plurality of end points of the second relay device individually connects to any of a plurality of second information processing devices over an expansion bus.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 26, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Masatoshi Kimura, Yuji Nakayama, Tomohiro Ishida
  • Publication number: 20200364153
    Abstract: A relay device includes end points to relay communication among information processing devices having root complexes connected to the end points. The relay device includes a hardware processor and circuitry. The hardware processor requests one of the devices to set an address space used to access a setting area for the one of the devices. The setting areas are areas in which access information for accessing public areas on memory spaces of the devices are set. The circuitry translates an address input from the one of the devices, based on a translation rule in which an address of the requested address space has been correlated with an address of the setting area for the one of the devices. The translation rule is stored in an area in which the devices are prohibited from performing rewriting.
    Type: Application
    Filed: April 1, 2020
    Publication date: November 19, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Yuji Nakayama, Masatoshi Kimura, Tomohiro Ishida
  • Publication number: 20200358637
    Abstract: An information processing system includes a relay device having an expansion bus and a plurality of platforms connected to each other via the expansion bus. An access source platform includes a first bridge driver that communicates with an access destination platform via the expansion bus, a first virtual LAN driver that recognizes the access destination platform as a platform on a virtual LAN, generates a first access request for a storage in the access destination platform, and transmits the first access request to the access destination platform via the first bridge driver, and a first block device driver that recognizes the storage as a storage connected to the access source platform, generates a second access request for the storage, and transmits the second access request to the access destination platform via the first bridge driver.
    Type: Application
    Filed: March 30, 2020
    Publication date: November 12, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Yuji Nakayama, Masatoshi Kimura
  • Publication number: 20200341928
    Abstract: In an information processing system, a first relay device includes first address ranges corresponding to first connection units of the first relay device connected to first information processing devices, and second address ranges corresponding to second connection units of a second relay device connected to second information processing devices, and transfers data for which a second address range is designated, from the first relay device to the second relay device. The second relay device includes third address ranges corresponding to the second connection units and fourth address ranges corresponding to the first connection units. When transferring data for which a second address range is designated, from the first relay device to the second relay device, the first relay device converts address information relating to the data to address information for designating a third address range and transfers the resultant address information to the second relay device.
    Type: Application
    Filed: March 5, 2020
    Publication date: October 29, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Yuji Nakayama, Masatoshi Kimura
  • Publication number: 20200341923
    Abstract: An information processing system includes: a plurality of information processing apparatuses that includes a main information processing apparatus and a plurality of sub information processing apparatuses, each of the plurality of information processing apparatuses being provided with a memory and a hardware processor; and a relay device that relays communication between the plurality of information processing apparatuses connected to each other over a plurality of connectors provided on a bus. In each of the plurality of sub information processing apparatuses, the memory stores connection information representing whether the main information processing apparatus or each of the other sub information processing apparatuses is a communication target of the corresponding sub information processing apparatus in units of the connectors. The hardware processor communicates with at least one of the plurality of information processing apparatuses based on the connection information.
    Type: Application
    Filed: March 12, 2020
    Publication date: October 29, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Yuji Nakayama, Masatoshi Kimura
  • Patent number: 10795851
    Abstract: A first end point and a second end point are provided. The first end point receives data from a root complex of a first platform among platforms, each serving as a computer that executes arithmetic processing. The second end point transfers the data to a root complex of a second platform among the platforms, the data to be transferred being received at the second end point by tunneling from the first end point.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 6, 2020
    Assignee: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Tomohiro Ishida, Masatoshi Kimura
  • Publication number: 20200257994
    Abstract: An inference processing system includes inference processing devices and performs inference processing such that a succeeding inference processing device performs inference processing to a result of inference processing by a preceding inference processing device.
    Type: Application
    Filed: January 23, 2020
    Publication date: August 13, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Yuichiro Ikeda, Masatoshi Kimura, Tomohiro Ishida, Kai Mihara
  • Publication number: 20200257993
    Abstract: An information processing system includes: a failure detector, a first failure handling unit and a second failure handling unit. The failure detector detects any of inference processing apparatuses in which a failure has occurred. The first failure handling unit causes another inference processing apparatus other than the inference processing apparatus in which the failure has occurred to execute an inference process of the inference processing apparatus in which the failure has occurred. The second failure handling unit inputs a result of an inference process at a preceding stage of the inference processing apparatus in which the failure has occurred to the another inference processing apparatus and outputs an inference result that the another inference processing apparatus generates based on the input inference result to an inference processing apparatus at a subsequent stage of the inference processing apparatus in which the failure has occurred.
    Type: Application
    Filed: January 23, 2020
    Publication date: August 13, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Yuichiro Ikeda, Masatoshi Kimura, Tomohiro Ishida, Kai Mihara
  • Publication number: 20200210201
    Abstract: An information processing system includes a plurality of information and a relay device. The information processing devices each includes a processor. The relay device connects the information processing devices via an expansion bus and relays communication between the information processing devices. The relay device includes a power supply controller that controls supply of power to the information processing devices, and performs control to shut off supply of power to the relay device and the information processing devices after detecting shutdown of all the information processing devices.
    Type: Application
    Filed: November 15, 2019
    Publication date: July 2, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Yuki Kawama, Masatoshi Kimura, Akira Takeuchi, Hiroki Teramoto
  • Publication number: 20200210254
    Abstract: An information processing system includes: a plurality of information processing devices each including a processor; and a relay device that connects the information processing devices via an expansion bus and relays communication between the information processing devices. The relay device includes a control unit that represents, for one of the information processing devices, the rest of the information processing devices, and communicates with the one of the information processing devices as an integrated information processing device of the relay device and the rest of the information processing devices.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 2, 2020
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Masatoshi Kimura, Tomohiro Ishida
  • Publication number: 20190354504
    Abstract: A first end point and a second end point are provided. The first end point receives data from a root complex of a first platform among platforms, each serving as a computer that executes arithmetic processing. The second end point transfers the data to a root complex of a second platform among the platforms, the data to be transferred being received at the second end point by tunneling from the first end point.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Tomohiro Ishida, Masatoshi Kimura
  • Publication number: 20190208030
    Abstract: A proxy device includes a request receiver that receives a request for acquisition of data from a requesting device; an acquirer that acquires the requested data from a server; storage that stores therein the data acquired from the server; and a controller that controls, upon no storage of the requested data in the storage, the acquirer to acquire, from the server, the requested data and other data stored in a same location of the storage.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 4, 2019
    Applicant: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Kazutoshi Taniyama, Masatoshi Kimura
  • Patent number: 10268175
    Abstract: A computer-implemented method includes obtaining one of image information of a recording medium placed in a sensing area and tag information attached to the recording medium; obtaining environmental control information corresponding to the obtained one of image information and tag information from a storage; and based on the obtained environmental control information, controlling one or more of a light-emitting device, a display device, an audio device, a temperature control device, an air-flow control device, a vibration device, and an aroma emitting device that are disposed around the sensing area.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 23, 2019
    Assignees: FUJITSU LIMITED, FUJTISU FACILITIES LIMITED
    Inventors: Yasushi Sugama, Yasushi Tateno, Masatoshi Kimura, Kazunori Maruyama, Tetsuo Yamamoto, Kota Ichinose
  • Patent number: 10074686
    Abstract: In a solid-state imaging device including a plurality of pixels each pixel including a plurality of photodiodes, it is prevented that an incidence angle of incident light on the solid-state imaging device becomes large in a pixel in an end of the solid-state imaging device, causing a difference in output between the two photodiodes in the pixel, and thus autofocus detection accuracy is deteriorated. Photodiodes extending in a longitudinal direction of a pixel allay section are provided in each pixel. The photodiodes in the pixel are arranged in a direction orthogonal to the longitudinal direction of the pixel allay section.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masatoshi Kimura
  • Patent number: 10062723
    Abstract: A semiconductor device is reduced in power consumption, the semiconductor device including a solid-state imaging device that includes pixels each having a plurality of light receiving elements. A pixel having first and second photodiodes is provided with a first transfer transistor that transfers charge in the first photodiode to a floating diffusion capacitance section, and a second transfer transistor that combines charge in the first photodiode and charge in the second photodiode, and transfers the combined charge to the floating diffusion capacitance section. Consequently, the semiconductor device is reduced in power required for activation of each transfer transistor in operation such as imaging with the solid-state imaging device.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 28, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Masatoshi Kimura