Patents by Inventor Masatoshi KOHNO

Masatoshi KOHNO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10431266
    Abstract: A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuyoshi Muraoka, Masami Masuda, Junya Matsuno, Masatoshi Kohno, Yuui Shimizu
  • Patent number: 10340857
    Abstract: According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junya Matsuno, Kazuyoshi Muraoka, Masami Masuda, Yuui Shimizu, Masatoshi Kohno, Masahiro Hosoya
  • Publication number: 20190088294
    Abstract: A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.
    Type: Application
    Filed: August 6, 2018
    Publication date: March 21, 2019
    Inventors: Kazuyoshi MURAOKA, Masami MASUDA, Junya MATSUNO, Masatoshi KOHNO, Yuui SHIMIZU
  • Publication number: 20180254750
    Abstract: According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.
    Type: Application
    Filed: September 8, 2017
    Publication date: September 6, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Junya MATSUNO, Kazuyoshi MURAOKA, Masami MASUDA, Yuui SHIMIZU, Masatoshi KOHNO, Masahiro HOSOYA
  • Publication number: 20170069377
    Abstract: According to one embodiment, a memory device includes a memory cell array configured to store data and a clock generator configured to generate a clock signal, the memory device outputs data held in the memory cell array in accordance with a timing of the clock signal, and the clock generator generates the clock signal with a substantially constant gradient each time a power supply is turned on.
    Type: Application
    Filed: March 1, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi KOHNO, Masami MASUDA, Hayato KONNO, Akihiro IMAMOTO
  • Publication number: 20150016205
    Abstract: A semiconductor circuit includes a first input section into which a first input signal is inputted, a second input section into which a second input signal is inputted, an output generation circuit which is connected to the first and second input sections and generates an output signal based on the input signals, an output section which outputs the output signal, and a current source which is connected to connection nodes between the input sections and the output generation circuit.
    Type: Application
    Filed: February 25, 2014
    Publication date: January 15, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masatoshi KOHNO, Masami MASUDA, Mikihiko ITO, Masaru KOYANAGI