Patents by Inventor Masatoshi Maeda

Masatoshi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936526
    Abstract: The network device information management apparatus includes: a log data acquisition unit configured to acquire log data from each of the plurality of devices, the log data including information about components of the plurality of devices; and an inventory information estimation unit configured to exclude a common portion of the log data before and after registration of the component to extract a component configuration indicating information about the component newly registered to the device, compare the extracted component configuration with the component configuration extracted from a component registered to another device, estimate the common portion as inventory information, and store the estimated inventory information in storage means.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: March 19, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masahiro Yokota, Masatoshi Namiki, Yuji Minato, Masaaki Inami, Daisaku Shimazaki, Hideki Maeda
  • Patent number: 10611934
    Abstract: A permanent adhesive composition for image sensors which provides an adhesive layer having excellent heat resistance and thermal shock resistance, and a bonding method and laminate using the permanent adhesive composition. The permanent adhesive composition for image sensors contains a thermosetting or photocurable resin containing a specific bifunctional (meth)acrylic acid ester-derived structural unit, a polymerizable monomer, and an antioxidant, and used to bond together a substrate and a support for the substrate. The bonding method includes bonding together a substrate and a support for the substrate using the permanent adhesive composition. The laminate is provided with a substrate, a support for the substrate, and an adhesive layer for bonding the substrate and the support together, and the adhesive layer is formed of the permanent adhesive composition.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 7, 2020
    Assignees: TOKYO OHKA KOGYO CO., LTD., NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventors: Tokunori Yamadaya, Hiroaki Takeuchi, Masatoshi Maeda, Kentaro Hayashi, Masayoshi Isozaki
  • Patent number: 10399254
    Abstract: A seamless mold manufacturing method of the invention is a seamless mold manufacturing method having the steps of forming a thermal reaction type resist layer on a sleeve-shaped mold, and exposing using a laser and developing the thermal reaction type resist layer and thereby forming a fine mold pattern, and is characterized in that the thermal reaction type resist layer is comprised of a thermal reaction type resist having a property of reacting in predetermined light intensity or more in a light intensity distribution in a spot diameter of the laser.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 3, 2019
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Masaru Suzuki, Yoshimichi Mitamura, Masatoshi Maeda
  • Patent number: 10358470
    Abstract: The object of the present invention is to provide a glycosylated polypeptide having uniform sugar chain structure which has interferon ? activity. It was found that a glycosylated polypeptide having uniform sugar chain structure as well as having interferon ? activity can be prepared by a method comprising a step of synthesizing a glycosylated peptide fragment and at least two peptide fragments and a step of linking the glycosylated peptide fragment and the at least two peptide fragments.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 23, 2019
    Assignee: GLYTECH, INC.
    Inventors: Izumi Sakamoto, Kazuhiro Fukae, Katsunari Tezuka, Keisuke Tazuru, Masatoshi Maeda, Yasuhiro Kajihara, Takashi Tsuji
  • Patent number: 10224921
    Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kanda, Koichi Yamazaki, Hiroshi Kuroiwa, Masatoshi Maeda, Tetsu Toda
  • Publication number: 20190002744
    Abstract: A permanent adhesive composition for image sensors which provides an adhesive layer having excellent heat resistance and thermal shock resistance, and a bonding method and laminate using the permanent adhesive composition. The permanent adhesive composition for image sensors contains a thermosetting or photocurable resin containing a specific bifunctional (meth)acrylic acid ester-derived structural unit, a polymerizable monomer, and an antioxidant, and used to bond together a substrate and a support for the substrate. The bonding method includes bonding together a substrate and a support for the substrate using the permanent adhesive composition. The laminate is provided with a substrate, a support for the substrate, and an adhesive layer for bonding the substrate and the support together, and the adhesive layer is formed of the permanent adhesive composition.
    Type: Application
    Filed: December 21, 2016
    Publication date: January 3, 2019
    Applicants: TOKYO OHKA KOGYO CO., LTD., NIPPON STEELE & SUMIKIN CHEMICAL CO., LTD.
    Inventors: Tokunori YAMADAYA, Hiroaki TAKEUCHI, Masatoshi MAEDA, Kentaro HAYASHI, Masayoshi ISOZAKI
  • Patent number: 10053499
    Abstract: The object of the present invention is to provide a polypeptide having interferon ? activity glycosylated with highly uniform sialylated sugar chains. The present invention is a glycosylated polypeptide, wherein the polypeptide is any polypeptide selected from the group consisting of the following (1) to (4); (1) a polypeptide consisting of the amino acid sequence represented by SEQ ID NO. 1, (2) a polypeptide having one or a few amino acids deleted, substituted, or added in the polypeptide consisting of the amino acid sequence represented by SEQ ID NO. 1, (3) a polypeptide that is an analog of interferon ?, and (4) a polypeptide having 80% or more homology to the polypeptide consisting of the amino acid sequence represented by SEQ ID NO. 1, in which amino acids at 4 to 6 locations are substituted with glycosylated amino acids, and wherein all of the non-reducing terminals of said sugar chain are sialylated.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: August 21, 2018
    Assignee: GLYTECH, INC.
    Inventors: Masaki Ohuchi, Mika Nishihara, Katsunari Tezuka, Masatoshi Maeda, Yasuhiro Kajihara, Izumi Sakamoto
  • Patent number: 9937264
    Abstract: [Problem] To provide a glycosylated polypeptide having an affinity to somatostatin receptors, and, compared to somatostatins, having improved in-blood stability. [Solution] The glycosylated polypeptide is characterized by at least one amino acid in a somatostatin or an analog thereof being replaced with a glycosylated amino acid.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 10, 2018
    Assignee: GLYTECH, INC.
    Inventors: Hirofumi Ochiai, Taiji Shimoda, Kazuhiro Fukae, Masatoshi Maeda, Kazuyuki Ishii, Kenta Yoshida, Katsunari Tezuka, Keisuke Tazuru
  • Publication number: 20180048257
    Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventors: Toshiya NOZAWA, Yoshitaro KONDO, Yusuke SUGAWARA, Shoichi KAMIMURA, Masatoshi MAEDA, Yasuhiro SHIRAI
  • Patent number: 9831816
    Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiya Nozawa, Yoshitaro Kondo, Yusuke Sugawara, Shoichi Kamimura, Masatoshi Maeda, Yasuhiro Shirai
  • Patent number: 9802996
    Abstract: [Problem] To provide a glycosylated polypeptide having affinity to somatostatin receptors and, compared to somatostatins, having improved in-blood stability. [Solution] The glycosylated polypeptide is characterized by at least two amino acids in a somatostatin or an analog thereof being replaced by glycosylated amino acids.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 31, 2017
    Assignee: Glytech, Inc.
    Inventors: Hirofumi Ochiai, Taiji Shimoda, Kazuhiro Fukae, Masatoshi Maeda, Keisuke Tazuru, Kenta Yoshida
  • Publication number: 20170170819
    Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Ryo KANDA, Koichi YAMAZAKI, Hiroshi KUROIWA, Masatoshi MAEDA, Tetsu TODA
  • Publication number: 20170157260
    Abstract: [Problem] To provide a glycosylated polypeptide having an affinity to somatostatin receptors, and, compared to somatostatins, having improved in-blood stability. [Solution] The glycosylated polypeptide is characterized by at least one amino acid in a somatostatin or an analogue thereof being replaced with a glycosylated amino acid.
    Type: Application
    Filed: July 8, 2016
    Publication date: June 8, 2017
    Inventors: Hirofumi Ochiai, Taiji Shimoda, Kazuhiro Fukae, Masatoshi Maeda, Kazuyuki Ishii, Kenta Yoshida, Katsunari Tezuka, Keisuke Tazuru
  • Patent number: 9621151
    Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been deteLutined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: April 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Kanda, Koichi Yamazaki, Hiroshi Kuroiwa, Masatoshi Maeda, Tetsu Toda
  • Publication number: 20170093325
    Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).
    Type: Application
    Filed: August 9, 2016
    Publication date: March 30, 2017
    Inventors: Toshiya NOZAWA, Yoshitaro KONDO, Yusuke SUGAWARA, Shoichi KAMIMURA, Masatoshi MAEDA, Yasuhiro SHIRAI
  • Publication number: 20170019093
    Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.
    Type: Application
    Filed: May 17, 2016
    Publication date: January 19, 2017
    Inventors: Ryo KANDA, Koichi Yamazaki, Hiroshi Kuroiwa, Masatoshi Maeda, Tetsu Toda
  • Publication number: 20160368961
    Abstract: [Problem] To provide a glycosylated polypeptide having affinity to somatostatin receptors and, compared to somatostatins, having improved in-blood stability. [Solution] The glycosylated polypeptide is characterized by at least two amino acids in a somatostatin or an analogue thereof being replaced by glycosylated amino acids.
    Type: Application
    Filed: July 19, 2016
    Publication date: December 22, 2016
    Inventors: Hirofumi Ochiai, Taiji Shimoda, Kazuhiro Fukae, Masatoshi Maeda, Keisuke Tazuru, Kenta Yoshida
  • Patent number: 9441024
    Abstract: [Problem] To provide a glycosylated polypeptide having affinity to somatostatin receptors and, compared to somatostatins, having improved in-blood stability. [Solution] The glycosylated polypeptide is characterized by at least two amino acids in a somatostatin or an analogue thereof being replaced by glycosylated amino acids.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: September 13, 2016
    Assignee: Glytech, Inc.
    Inventors: Hirofumi Ochiai, Taiji Shimoda, Kazuhiro Fukae, Masatoshi Maeda, Keisuke Tazuru, Kenta Yoshida
  • Patent number: 9422357
    Abstract: [Problem] To provide a glycosylated polypeptide having an affinity to somatostatin receptors, and, compared to somatostatins, having improved in-blood stability. [Solution] The glycosylated polypeptide is characterized by at least one amino acid in a somatostatin or an analog thereof being replaced with a glycosylated amino acid.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: August 23, 2016
    Assignee: Glytech, Inc.
    Inventors: Hirofumi Ochiai, Taiji Shimoda, Kazuhiro Fukae, Masatoshi Maeda, Kazuyuki Ishii, Kenta Yoshida, Katsunari Tezuka, Keisuke Tazuru
  • Patent number: 9391236
    Abstract: To provide a substrate for optics provided with a fine-structure product which improves luminous efficiency of an LED while improving internal quantum efficiency IQE by decreasing the number of dislocation defects in a semiconductor layer, a substrate for optics (1) is provided with a fine-structure layer (12) including dots comprised of a plurality of convex portions (13) extending in the direction of from the main surface of a substrate (11) to outside the surface, where the fine-structure layer (12) has a plurality of dot lines (13-1 to 13-N) in which a plurality of dots is arranged with a pitch Py in the first direction in the main surface of the substrate (11), while having the plurality of dot lines in which a plurality of dots is arranged with a pitch Px in the second direction orthogonal to the first direction in the main surface of the substrate (11), one of the pitch Py and the pitch Px is a constant interval of nano-order, while the other one is an inconstant interval of nano-order, or both are inc
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: July 12, 2016
    Assignee: ASAHI KASEI E-MATERIALS CORPORATION
    Inventors: Fujito Yamaguchi, Jun Koike, Masatoshi Maeda