Abstract: Each of a plurality of semiconductor chips comprises an integrated circuit region and a plurality of electrodes for electrical connection to outside. The electrodes are disposed on a surface of each of the semiconductor chips in a predetermined pattern. A distance between a left side of each of the semiconductor chips and each of the electrodes, and a distance between a right side of each of said semiconductor chips and each of the electrodes are predetermined distances, respectively.

Abstract: A memory tester including an algorithmic pattern generator (ALPG) for generating a test pattern as a digital signal based on vector data is provided with a digital-to-analog converter built in the memory tester or provided outside the memory tester. Thus, the function of a device under test (DUT) having the analog-to-digital converting function can be verified. In other words, an address signal included in the test pattern generated in the ALPG is used for generating an analog signal to be input to the DUT having the analog-to-digital converting function, not for address designation. A control unit compares an output digital signal generated in the DUT with the address signal generated in the ALPG as a test digital signal to detect the degree of agreement between these signals, thereby verifying the analog-to-digital converting function of the DUT.