Abstract: This image generation device is provided with: an image acquisition unit that acquires a rear-side image of the rear side of a vehicle; and an image generation unit. When the rear-side image includes an overlapped portion where an image region, in which an auxiliary line for assisting in the backward driving of the vehicle is overlaid, overlaps an image region in which a specific target is positioned, the image generation unit generates, in at least the overlapped portion, an image in which the auxiliary line is not overlaid or is overlaid in a semi-transparent state; and when the rear-side image does not include the overlapped portion, the image generation unit generates an image in which the auxiliary line is overlaid on the rear-side image.

Abstract: This image generation device is provided with: an image acquisition unit that acquires a rear-side image of the rear side of a vehicle; and an image generation unit. When the rear-side image includes an overlapped portion where an image region, in which an auxiliary line for assisting in the backward driving of the vehicle is overlaid, overlaps an image region in which a specific target is positioned, the image generation unit generates, in at least the overlapped portion, an image in which the auxiliary line is not overlaid or is overlaid in a semi-transparent state; and when the rear-side image does not include the overlapped portion, the image generation unit generates an image in which the auxiliary line is overlaid on the rear-side image.

Abstract: An arbitration circuit 108 receives a read/write request from a master 101, such as a CPU, in which low latency is required, at a regular interval, such that the master 101 performs memory access with low latency. A remaining band which is not used by the master 101 is allocated to masters 102 and 103, such as a DMA controller, in which a wideband is required, thereby ensuring a necessary band. When a read/write request is retained in a buffer 119 of a slave 118, the arbitration circuit 108 suppresses the acceptance of the read/write requests from the masters 102 and 103 having low priority. Therefore, it is possible to provide a bus arbitration apparatus capable of transmitting a request from a specific master to a slave with low latency, and to ensure a band necessary for another master.

Abstract: An A/D converter that supports multi-mode and that can minimize power consumption is provided. A hybrid A/D converter comprises: hybrid stages composed of 1.5-bit A/D converter for pipeline use that convert analogue input signals into digital signals; 1/1.5-bit D/A converters that switch between pipeline use and delta-sigma modulation use according to the mode in use; analogue adders that subtract output of the 1/1.5 D/A converters from the analogue input signals; and analogue operation circuits that receive as input the output of the analogue adders and function as amplifiers in pipeline mode and as integrators in delta-sigma mode.

Abstract: A DC offset cancel circuit includes an analog adder 1 to whose one input a baseband analog signal output from a high-frequency reception section is input and to whose other input an analog correction signal output from a D/A converter 7 is input, and which corrects the reference voltage value of the baseband analog signal analogically to cancel a DC offset, an adder 3 which has the output of the A/D converter 2 as its one input and subtracts the lower bits of a sample value stored in a memory 6 to be described later as a DC offset value from the input value and outputs the resultant value, a control circuit 5 which outputs an output digital value of the A/D converter 2 as a sample value to the memory 6, and a D/A converter 7 which converts a digital value of the upper bits of a sample value stored in the memory 6 to an analog correction signal and outputs the analog correction signal to the analog adder 1.

Abstract: An A/D converter that supports multi-mode and that can minimize power consumption is provided. A hybrid A/D converter 100 comprises: hybrid stages 101 to 103 composed of 1.5-bit A/D converter 111, 121 and 131 for pipeline use that convert analogue input signals into digital signals; 1/1.5-bit D/A converters 112, 122 and 132 that switch between pipeline use and delta-sigma modulation use according to the mode in use; analogue adders 113, 123 and 133 that subtract output of the 1/1.5 D/A converters 112, 122 and 132 from the analogue input signals; and analogue operation circuits 114, 124 and 134 that receive as input the output of the analogue adders 113, 123 and 133 and function as amplifiers in pipeline mode and as integrators in delta-sigma mode.

Abstract: A DC offset cancel circuit includes an analog adder 1 to whose one input a baseband analog signal output from a high-frequency reception section is input and to whose other input an analog correction signal output from a D/A converter 7 is input, and which corrects the reference voltage value of the baseband analog signal analogically to cancel a DC offset, an adder 3 which has the output of the A/D converter 2 as its one input and subtracts the lower bits of a sample value stored in a memory 6 to be described later as a DC offset value from the input value and outputs the resultant value, a control circuit 5 which outputs an output digital value of the A/D converter 2 as a sample value to the memory 6, and a D/A converter 7 which converts a digital value of the upper bits of a sample value stored in the memory 6 to an analog correction signal and outputs the analog correction signal to the analog adder 1.

Abstract: A reference voltage output terminal of first and second reference voltage generating circuits is connected to a first current input terminal of a current mirror circuit of an operational amplifier by a diode element. At the time of start-up, a reference voltage generated on the reference voltage output terminal is 0 V. Consequently, a current flows to the diode element and an offset voltage Voff is generated on the operational amplifier so that a malfunction point is caused to disappear. Accordingly, in the case where a normal operation point on which a reference voltage having an expected value is generated and a malfunction point on which an operation is stabilized with a reference voltage having a value less than the expected value are present, the generated reference voltage is raised at the time of start-up, passes through the malfunction point to reach an expected voltage value on the normal operation point and becomes stabilized.

Abstract: In a multiprocessor system, a data transferring port into which data can be written only when no data is stored and from which data can be read only when it is stored is provided, and the port itself is caused to perform an exclusion control, whereby that processor of a plurality of processors which has once acquired a bus mastership is prevented from making another bus use request until the bus use requests of the other processors run out.