Patents by Inventor Masatoshi Nanjo
Masatoshi Nanjo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7727810Abstract: A method of dividing a wafer having a plurality of areas, which are sectioned by the streets formed on the front surface in a lattice pattern and a plurality of devices, which are formed in the sectioned areas, along streets, the method comprising a first cutting step for holding the front surface of the wafer on a chuck table of a cutting machine and forming a first groove having a depth that is about half of the thickness of the wafer, along the streets from the rear surface of the wafer; a second cutting step for holding the rear surface of the wafer on a chuck table and forming a second groove which does not reach the first groove, along the streets from the front surface of the wafer; and a dividing step for breaking an uncut portion between the first groove and the second groove by exerting external force along the streets of the wafer, on which the first grooves and the second grooves have been formed.Type: GrantFiled: July 21, 2006Date of Patent: June 1, 2010Assignee: Disco CorporationInventors: Kazuhisa Arai, Masatoshi Nanjo
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Patent number: 7592235Abstract: A wafer, in which a plurality of rectangular regions are defined on the face of the wafer by streets arranged in a lattice pattern, and a semiconductor memory element is disposed in each of the rectangular regions, is divided along the streets to separate the rectangular regions individually, thereby forming a plurality of semiconductor devices. Before the wafer is divided along the streets, a strained layer having a thickness of 0.20 ?m or less, especially 0.05 to 0.20 ?m, is formed in the back of the wafer. The strained layer is formed by grinding the back of the semiconductor wafer by a grinding member formed by bonding diamond abrasive grains having a grain size of 4 ?m or less by a bonding material.Type: GrantFiled: April 21, 2005Date of Patent: September 22, 2009Assignee: Disco CorporationInventor: Masatoshi Nanjo
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Patent number: 7459767Abstract: A wafer, in which a plurality of rectangular regions are defined on the face of the wafer by streets arranged in a lattice pattern, and a semiconductor memory element is disposed in each of the rectangular regions, is divided along the streets to separate the rectangular regions individually, thereby forming a plurality of semiconductor devices. Before the wafer is divided along the streets, a strained layer having a thickness of 0.20 ?m or less, especially 0.05 to 0.20 ?m, is formed in the back of the wafer. The strained layer is formed by grinding the back of the semiconductor wafer by a grinding member formed by bonding diamond abrasive grains having a grain size of 4 ?m or less by a bonding material.Type: GrantFiled: May 18, 2006Date of Patent: December 2, 2008Assignee: Disco CorporationInventor: Masatoshi Nanjo
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Patent number: 7325692Abstract: A cassette for storing a plurality of semiconductor wafers with a space in the vertical direction has a plurality of support plates which are provided spaced apart from one another in the vertical direction. A receiving cut-out having a shape corresponding to the shape of an adsorber for suction-holding a semiconductor wafer are formed in the front half portion of each of the support plates. The cassette further comprises separation plates between adjacent support plates.Type: GrantFiled: November 26, 2002Date of Patent: February 5, 2008Assignee: Disco CorporationInventor: Masatoshi Nanjo
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Publication number: 20070029684Abstract: A method of dividing a wafer having a plurality of areas, which are sectioned by the streets formed on the front surface in a lattice pattern and a plurality of devices, which are formed in the sectioned areas, along streets, the method comprising a first cutting step for holding the front surface of the wafer on a chuck table of a cutting machine and forming a first groove having a depth that is about half of the thickness of the wafer, along the streets from the rear surface of the wafer; a second cutting step for holding the rear surface of the wafer on a chuck table and forming a second groove which does not reach the first groove, along the streets from the front surface of the wafer; and a dividing step for breaking an uncut portion between the first groove and the second groove by exerting external force along the streets of the wafer, on which the first grooves and the second grooves have been formed.Type: ApplicationFiled: July 21, 2006Publication date: February 8, 2007Inventors: Kazuhisa Arai, Masatoshi Nanjo
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Patent number: 7172950Abstract: In manufacturing thinned semiconductor chips by grinding a semiconductor wafer supported on a rigid support substrate, in order to remove the semiconductor wafer or semiconductor chips from the support substrate without damage to the semiconductor wafer or semiconductor chips, a semiconductor wafer at its surface is bonded on a light-transmissive support substrate through an adhesive layer having an adhesion force that is reduced upon exposure to light radiation, thereby exposing the back surface of the semiconductor wafer. A tape is bonded to the backside of the semiconductor wafer integrated with the support substrate after grinding, wherein the tape is supported at the periphery. Before or after bonding of the tape, light radiation is applied to the adhesive layer at a side close to the support substrate to reduce the adhesion force in the adhesion layer.Type: GrantFiled: March 24, 2004Date of Patent: February 6, 2007Assignees: Kansai Paint Co., Ltd., Disco CorporationInventors: Kouji Takezoe, Akito Ichikawa, Koichi Tamura, Masahiko Kitamura, Koichi Yajima, Masatoshi Nanjo, Shinichi Namioka
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Publication number: 20060208329Abstract: A wafer, in which a plurality of rectangular regions are defined on the face of the wafer by streets arranged in a lattice pattern, and a semiconductor memory element is disposed in each of the rectangular regions, is divided along the streets to separate the rectangular regions individually, thereby forming a plurality of semiconductor devices. Before the wafer is divided along the streets, a strained layer having a thickness of 0.20 ?m or less, especially 0.05 to 0.20 ?m, is formed in the back of the wafer. The strained layer is formed by grinding the back of the semiconductor wafer by a grinding member formed by bonding diamond abrasive grains having a grain size of 4 ?m or less by a bonding material.Type: ApplicationFiled: May 18, 2006Publication date: September 21, 2006Inventor: Masatoshi Nanjo
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Publication number: 20050255674Abstract: A wafer, in which a plurality of rectangular regions are defined on the face of the wafer by streets arranged in a lattice pattern, and a semiconductor memory element is disposed in each of the rectangular regions, is divided along the streets to separate the rectangular regions individually, thereby forming a plurality of semiconductor devices. Before the wafer is divided along the streets, a strained layer having a thickness of 0.20 ?m or less, especially 0.05 to 0.20 ?m, is formed in the back of the wafer. The strained layer is formed by grinding the back of the semiconductor wafer by a grinding member formed by bonding diamond abrasive grains having a grain size of 4 ?m or less by a bonding material.Type: ApplicationFiled: April 21, 2005Publication date: November 17, 2005Inventor: Masatoshi Nanjo
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Patent number: 6943045Abstract: A semiconductor wafer protecting unit which enables a semiconductor wafer to be handled as required, without breakage of the semiconductor wafer, even when the back of the semiconductor wafer is ground to decrease the thickness of the semiconductor wafer markedly; and a semiconductor wafer processing method using such a semiconductor wafer protecting unit. The semiconductor wafer protecting unit is composed of a magnetized tape having one surface with tackiness, and a magnetic substrate having many pores formed at least in a central zone thereof.Type: GrantFiled: February 27, 2003Date of Patent: September 13, 2005Assignee: Disco CorporationInventors: Masahiko Kitamura, Masatoshi Nanjo, Kouichi Yajima, Shinichi Namioka
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Patent number: 6927416Abstract: A wafer support plate comprises a support surface on which a semiconductor wafer is supported, and a crystal orientation mark which indicates the crystal orientation of the semiconductor wafer. Even the semiconductor wafer thinned by grinding can be stably held on the support surface, and the crystal orientation can be recognized even when the outer periphery of the semiconductor wafer has chipped.Type: GrantFiled: December 17, 2003Date of Patent: August 9, 2005Assignee: Disco CorporationInventors: Kazuhisa Arai, Masatoshi Nanjo, Masahiko Kitamura, Shinichi Namioka, Koichi Yajima
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Patent number: 6869830Abstract: Prior to a grinding step, the front surface of a semiconductor wafer is stuck on a substrate to be mounted on the substrate. The transfer step of mounting the semiconductor wafer on a frame having a mounting opening in its center portion through a mounting tape and removing the substrate from the front surface of the semiconductor wafer is carried out between the grinding step and the subsequent treating step. The substrate is formed of a laminate consisting of a plurality of layers.Type: GrantFiled: September 24, 2002Date of Patent: March 22, 2005Assignee: Disco CorporationInventor: Masatoshi Nanjo
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Publication number: 20040256284Abstract: A cassette for storing a plurality of semiconductor wafers with a space in the vertical direction has a plurality of support plates which are provided spaced apart from one another in the vertical direction. A receiving cut-out having a shape corresponding to the shape of an adsorber for suction-holding a semiconductor wafer are formed in the front half portion of each of the support plates. The cassette further comprises separation plates between adjacent support plates.Type: ApplicationFiled: August 26, 2003Publication date: December 23, 2004Inventor: Masatoshi Nanjo
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Publication number: 20040235269Abstract: A semiconductor wafer protecting unit which enables a semiconductor wafer to be handled as required, without breakage of the semiconductor wafer, even when the back of the semiconductor wafer is ground to decrease the thickness of the semiconductor wafer markedly; and a semiconductor wafer processing method using such a semiconductor wafer protecting unit. The semiconductor wafer protecting unit is composed of a magnetized tape having one surface with tackiness, and a magnetic substrate having many pores formed at least in a central zone thereof.Type: ApplicationFiled: August 20, 2003Publication date: November 25, 2004Inventors: Masahiko Kitamura, Masatoshi Nanjo
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Publication number: 20040192012Abstract: In manufacturing thinned semiconductor chips by grinding a semiconductor wafer supported on a rigid support substrate, in order to remove semiconductor wafer or semiconductor chips from the support substrate without damage to the semiconductor wafer or semiconductor chips, a semiconductor wafer at its surface is bonded on a light-transmissive support substrate through an adhesive layer having an adhesion force to reduce upon exposed to light radiation, thereby exposing the back surface of the semiconductor wafer. A tape is bonded to the backside of the semiconductor wafer integrated with the support substrate of after grinding, wherein the tape is supported at the periphery. Before or after bonding of the tape, light radiation is applied to the adhesive layer at a side close to the support substrate to reduce the adhesion force in the adhesion layer.Type: ApplicationFiled: March 24, 2004Publication date: September 30, 2004Inventors: Kouji Takezoe, Akito Ichikawa, Koichi Tamura, Masahiko Kitamura, Koichi Yajima, Masatoshi Nanjo, Shinichi Namioka
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Publication number: 20040124413Abstract: A wafer support plate comprises a support surface on which a semiconductor wafer is supported, and a crystal orientation mark which indicates the crystal orientation of the semiconductor wafer. Even the semiconductor wafer thinned by grinding can be stably held on the support surface, and the crystal orientation can be recognized even when the outer periphery of the semiconductor wafer has chipped.Type: ApplicationFiled: December 17, 2003Publication date: July 1, 2004Inventors: Kazuhisa Arai, Masatoshi Nanjo, Masahiko Kitamura, Shinichi Namioka, Koichi Yajima
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Publication number: 20040092108Abstract: A method of processing a semiconductor wafer having a large number of rectangular areas sectioned by streets arranged in a lattice form on the front surface, circuits being formed in the respective areas. This method comprises the step of mounting a semiconductor wafer on a protective substrate in such a manner that the front surface of the semiconductor wafer is opposed to one side of the protective substrate having a large number of pores in at least its central area prior to the grinding of the back surface of the semiconductor wafer.Type: ApplicationFiled: October 28, 2003Publication date: May 13, 2004Inventors: Kouichi Yajima, Masahiko Kitamura, Shinichi Namioka, Masatoshi Nanjo
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Publication number: 20030102557Abstract: Prior to a grinding step, the front surface of a semiconductor wafer is stuck on a substrate to be mounted on the substrate. The transfer step of mounting the semiconductor wafer on a frame having a mounting opening in its center portion through a mounting tape and removing the substrate from the front surface of the semiconductor wafer is carried out between the grinding step and the subsequent treating step. The substrate is formed of a laminate consisting of a plurality of layers.Type: ApplicationFiled: September 24, 2002Publication date: June 5, 2003Inventor: Masatoshi Nanjo