Abstract: An information processing apparatus, including (1) a classification device configured to classify a state of an observation target using a learning result based on sensor information received from a multiple sensor terminals; and (2) a transmission control model constructing device configured to determine a necessity for transmission of sensor information for each sensor terminal based on communication cost of sensor information and classification accuracy of the classification device, wherein the classification device classifies the state of the observation target based on sensor information transmitted based on the necessity of transmission determined by the transmission control model constructing device.

Abstract: The invention provides an object detection device including a statistical model estimation section that, using a Doppler signal in a specific period of time for a given reflecting object, or using data obtained by performing a specific data conversion on the Doppler signal, estimates a statistical model expressing time series fluctuations in the Doppler signal or in the data, and a determination section that determines whether or not there is an aperiodically moving object present at the reflecting object based on incompatibility between the statistical model estimated by the statistical model estimation section and time series fluctuations in the Doppler signal or in the data.

Abstract: A radio communication system in which radio communication terminals can efficiently transmit and receive data with each other suppressing the amount of data held by each of them. Each radio communication terminal can calculate an average delivery delay time of deliver data based on the degree of proximity to an adjacent radio communication terminal and transmit data delivery path information containing this and, for each data delivery path information received from another radio communication terminal, calculate a total average delivery delay time for delivery to a destination radio communication terminal based on the average delivery delay time contained in the data delivery path information and the average delivery delay time calculated by itself and, in response to the arrival of a data delivery time, transmit deliver data toward the destination radio communication terminal via the delivery path associated with the smallest total average delivery delay time.

Abstract: An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.

Abstract: An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.

Abstract: A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.

Abstract: Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second reconfigurable circuit which is connected to output side of a register file as part of processing unit and wherein a circuit structure thereof can be changed according to an external signal is preliminarily provided. For special use, to achieve a predetermined operating function, the second reconfigurable circuit is reconstructed by the external signal. Further, a particular instruction corresponding to the predetermined operating function is set, and the first reconfigurable circuit is so reconstructed by an external signal that when the particular instruction is inputted, a corresponding control signal is outputted.

Abstract: A reconfigurable circuit is reconstructed to three or more operating circuit blocks. Upon testing, the same data is inputted to each of the reconstructed operating circuit blocks. A majority circuit formed in the reconfigurable circuit compares results of operations of the operating circuit blocks and outputs information indicating which of the operating circuit blocks is in trouble.

Abstract: A model of architecture of a processor is called an architecture template. Because a designer selects an architecture template of a special purpose processor which is suitable for an objective signal processing algorithm from an architecture template library, a special purpose processor which is the most suitable for any signal algorithm can be synthesized. Moreover, by providing a method of creating an architecture template simply, even if there is no desirable architecture template, an objective architecture template can be synthesized for a short time.

Abstract: A digital signal processing apparatus comprises a sensor, a multi-valued binary level signal generator, a wavelet transform section, and a post processor. The signal generator receives analog signals output from the sensor and converts them to multi-valued binary level signals. The wavelet transform section has fundamental elements and threshold devices. The fundamental elements are provided at the nodes of a tree structure. Each threshold device is designed to receive at least two multi-valued signals and to output one binary signal, it receives the coefficients of the scaling functions output from the fundamental elements provided at the same level of the tree structure, for extracting the feature of the analog signal. The output signals of the wavelet transform section, i.e., the results of the wavelet transform, are input to the post processor. The apparatus can therefore perform signal processing including wavelet transform, at high speed without using large-scale hardware.

Abstract: A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.

Abstract: A high-level synthesis apparatus synthesizes a large-scale logic circuit. The apparatus has a unit for generating a control description graph according to a behavioral description graph written in a behavioral description language; a unit for sorting the control description graph according to control conditions and extracting single flows including partial graphs or closed loops from the sorted control description graph; a unit for providing an initial circuit; a unit for dividing the single flows into execution steps; a unit for allocating hardware parts of the initial circuit to the execution steps; and a unit for converting each of the single flows into a finite state machine and combining the finite state machines into one. This apparatus optimizes each single flow and adds parts to or modifies the initial circuit, to synthesize a large-scale circuit.

Abstract: A heuristic control system and method for use with a computer-aided design, capable of learning complicated control and achieving an optimizing task with a fewer number of iteration. The heuristic control system includes: rule-based system for choosing and evaluating a rule among a plurality of given rules; training system for choosing strongly a rule whose evaluation result is favorable based on a predetermined value which evaluates an evaluation result of the rule-based system, and for generating a learning pattern; and neural network for designing an optimized circuit based on a signal fed from the training system and for sending a resultant signal to the rule-based system for another iteration of heuristic control.

Abstract: Disclosed is an LSI design support system for making a functional design of LSI using a graphic input method. This system comprises a state transition diagram preparation portion for preparing a state transition diagram, state transition table preparation portion for preparing a state transition table, and a state-operation circuit diagram preparation portion for preparing a state-operation circuit diagram. Data from these preparation portions are examined therebetween and the results are displayed at the same time on a picture plane so that a designer can efficiently make a design on circuit operation including its state transition. Also disclosed is another LSI design support system.

Abstract: Disclosed is a design aid apparatus for integrated circuits, which includes an input section for inputting design data, concerning a circuit to be designed, by means of diagrams or by means of language descriptions; a design section for designing a circuit in accordance with language input design data so as to prepare language design circuit data, and for preparing diagram design circuit data corresponding to the language design circuit data, or for designing a circuit in accordance with diagram input design data so as to prepare diagram design circuit data, and for preparing language design circuit data corresponding to the diagram design circuit data; and a holding section for storing and holding both the language design circuit data and the diagram design circuit data from the design section.

Abstract: A process system more efficiently processes information composed of significant information and insignificant information. The system includes an input portion which selects significant information from information inputted through a plurality of input terminals. The system recognizes each significance degree which indicate a time duration of the significant information as a value showing an input state. An operation circuit carries out a predetermined logic operation for the significant information propagated from the input portion. An output portion compares each significance degree of the significant information obtained from the logic operation results of the operation circuit with a predetermined threshold value. The output portion recognizes each significance degree obtained from the logic operation result as a value indicating an output state.

Abstract: Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them.