Patents by Inventor Masatoshi Shibasaki

Masatoshi Shibasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8831040
    Abstract: A transfer device according to an embodiment transfers blocks generated by dividing a frame into pieces of data and adding a synchronization header each of the pieces of data. The blocks comprise a first, second and third blocks in this order. The transfer device is configured to acquire a first synchronization header in the first block, a second synchronization header in the second block and a third synchronization header in the third block, judge, in a case where a value of the second synchronization header is incorrect, as to whether or not the value of the second synchronization header can be estimated based on the first and the third synchronization headers so that the second block is consistent with the first and third blocks, and correct the second synchronization header into the estimated value.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: September 9, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Nakajima, Masatoshi Shibasaki, Yukihisa Tamura
  • Patent number: 8634426
    Abstract: When multiple SDH/SONET frame are accumulated and then lower-order path information removed from multiple frames is multiplexed into the same packet to achieve better transmission efficiency during packetization, the delay for accumulating increases. Disclosed is a transmission device that packetizes an SDH/SONET lower-order path with timing which is an integer factor of 1 cycle of the SDH frame. In this case, the destination loads the same multiple lower-order path in one packet. The result is that delay time accompanying lower-order path packetization is kept to less than the time of 1 cycle of the SDH frame, and the efficiency with which lower-order paths are accommodated in packets is further increased. The result is that improved transmission efficiency is realized.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Nogi, Masatoshi Shibasaki, Naohiro Sakakida, Yoshihiro Ashi, Kazutaka Sakai
  • Patent number: 8416681
    Abstract: A network system having duplicate lines of a primary system and a backup system between a transmitter apparatus and a receiver apparatus is provided. Each of the transmitter apparatus and the receiver apparatus includes an arithmetic operator for conducting a BIP-8 arithmetic operation and a CRC arithmetic operation on an input signal and thereby detecting a bit error. The transmitter apparatus transmits data to both lines. The receiver apparatus includes a switcher. When a bit error is detected in received data of the primary system. the switcher switches control of the primary system and the backup system. Hitless protection switching of a VC path is executed.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 9, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yukihisa Tamura, Masatoshi Shibasaki, Mitsuru Asayama, Tsutomu Kawaizumi, Kenji Okamoto
  • Patent number: 8306066
    Abstract: A transmission device comprises first interfaces each of which receives time-division multiplexed signals from an external device in units of frames, a switch which is connected with the first interfaces and sets paths of the signals received from the first interface in regard to each packet, and second interfaces each of which is connected with the switch, receives the signals from the first interface via the switch, and transmits the received signals to a different transmission device in units of packets. The first interface selects signals having the same destination from the signals contained in the received frame and stores the selected signals having the same destination in one packet.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: November 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Shibasaki, Takao Fukushima, Toshiyuki Atsumi, Yoshio Nogi
  • Patent number: 8149868
    Abstract: A circuit capable of processing signals of different signal types is provided for identifying the signal type by the signal type setting from an administrator or by the implementation of the optical module, thereby selecting a signal processor to be used. An OTN frame standardized by ITU is used in a fixed manner independent of the signal type to be accommodated, while a corresponding SDH/SONET frame standardized by ITU is used for signal accommodation.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hidemasa Narita, Takao Fukushima, Masatoshi Shibasaki, Toshiyuki Atsumi, Yukihisa Tamura
  • Publication number: 20120027023
    Abstract: When multiple SDH/SONET frame are accumulated and then lower-order path information removed from multiple frames is multiplexed into the same packet to achieve better transmission efficiency during packetization, the delay for accumulating increases. Disclosed is a transmission device that packetizes an SDH/SONET lower-order path with timing which is an integer factor of 1 cycle of the SDH frame. In this case, the destination loads the same multiple lower-order path in one packet. The result is that delay time accompanying lower-order path packetization is kept to less than the time of 1 cycle of the SDH frame, and the efficiency with which lower-order paths are accommodated in packets is further increased. The result is that improved transmission efficiency is realized.
    Type: Application
    Filed: November 14, 2008
    Publication date: February 2, 2012
    Inventors: Yoshio Nogi, Masatoshi Shibasaki, Naohiro Sakakida, Yoshihiro Ashi, Kazutaka Sakai
  • Publication number: 20110216782
    Abstract: A transfer device according to an embodiment transfers blocks generated by dividing a frame into pieces of data and adding a synchronization header each of the pieces of data. The blocks comprise a first, second and third blocks in this order. The transfer device is configured to acquire a first synchronization header in the first block, a second synchronization header in the second block and a third synchronization header in the third block, judge, in a case where a value of the second synchronization header is incorrect, as to whether or not the value of the second synchronization header can be estimated based on the first and the third synchronization headers so that the second block is consistent with the first and third blocks, and correct the second synchronization header into the estimated value.
    Type: Application
    Filed: February 4, 2011
    Publication date: September 8, 2011
    Inventors: TETSUYA NAKAJIMA, Masatoshi Shibasaki, Yukihisa Tamura
  • Publication number: 20110214008
    Abstract: A network system having duplicate lines of a primary system and a backup system between a transmitter apparatus and a receiver apparatus is provided. Each of the transmitter apparatus and the receiver apparatus includes an arithmetic operator for conducting a BIP-8 arithmetic operation and a CRC arithmetic operation on an input signal and thereby detecting a bit error. The transmitter apparatus transmits data to both lines. The receiver apparatus includes a switcher. When a bit error is detected in received data of the primary system. the switcher switches control of the primary system and the backup system.
    Type: Application
    Filed: January 25, 2011
    Publication date: September 1, 2011
    Inventors: YUKIHISA TAMURA, Masatoshi SHIBASAKI, Mitsuru ASAYAMA, Tsutomu KAWAIZUMI, Kenji OKAMOTO
  • Publication number: 20110164622
    Abstract: An interface unit for processing a first signal and a second signal, the second signal set to different transmission rate from the first signal and/or a different signal type from the first signal, including a plurality of interface panels, each of the plurality of interface panels including: a storage device which stores a first logic circuit data corresponding to the first signal and a second logic circuit data corresponding to the second signal, a configuration function unit which controls to select the first logic circuit data or the second logic circuit data, and a programmable logic circuit which reconfigures the first logic circuit data or the second logic circuit data based on a selection by the configuration function unit.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 7, 2011
    Inventors: Yukihisa TAMURA, Manabu Makino, Koji Takatori, Hiromi Murakami, Yoshimasa Kusano, Toshiyuki Atsumi, Masatoshi Shibasaki
  • Patent number: 7912373
    Abstract: In a known wavelength multiplexer, optical signals to pass are passed with their wavelengths held identical. Therefore, unless an unused wavelength common to all zones exists in case of setting an optical channel, the channel cannot be set. According to the present invention, a drop/add type wavelength multiplexer includes a wavelength converting section (50 in FIG. 5) which converts the wavelengths of optical signals to pass from the input side of the multiplexer to the output side thereof. In a network employing the wavelength multiplexers at individual nodes, a new optical channel can be easily set by utilizing wavelengths not used at the nodes.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: March 22, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Yajima, Takashi Mori, Masatoshi Shibasaki
  • Patent number: 7830924
    Abstract: A unit timing signal synchronized with a high-order transmission frame is used for measuring a difference between the number of data pieces of a client signal mapped to the high-frequency frame and the number of data pieces of the output client signal by integrating the difference therebetween for each unit timing signal. Then stuffing and de-stuffing operations are performed so that a integration result is zero.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: November 9, 2010
    Assignee: Hitachi Communication Technologies, Ltd.
    Inventors: Kenji Kawamura, Takashi Funada, Masatoshi Shibasaki, Yoshimasa Kusano, Yusuke Honda, Hiromi Murakami
  • Publication number: 20100226370
    Abstract: When label switching is performed on a conventional MPLS packet, a bit error may occur in an MPLS label header of the MPLS packet and user data may misdelivered. To avoid such misdelivery of the user data, an HEC function is attached to the MPLS label header.
    Type: Application
    Filed: November 4, 2009
    Publication date: September 9, 2010
    Inventors: Yukihisa TAMURA, Koji TAKATORI, Masatoshi SHIBASAKI, Toshiyuki ATSUMI
  • Patent number: 7756045
    Abstract: An optical signal connection apparatus comprising a first node and a second node connects first and second optical signal transmission lines to respective first and second routers. The first node includes a first port coupled to the first router via the first optical signal transmission line, and is configured to handle a first type of optical signals associated with the first router. The second node includes a second port coupled to the second router via the second optical signal transmission line, and is configured to handle a second type of optical signals associated with the second router. The information regarding the first type of optical signal is compared with information regarding the second type of optical signal to determine whether or not the first and second optical signal transmission lines are compatible to each other.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: July 13, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Atsumi, Masatoshi Shibasaki, Teruhisa Takano
  • Publication number: 20100111111
    Abstract: A transmission device comprises first interfaces each of which receives time-division multiplexed signals from an external device in units of frames, a switch which is connected with the first interfaces and sets paths of the signals received from the first interface in regard to each packet, and second interfaces each of which is connected with the switch, receives the signals from the first interface via the switch, and transmits the received signals to a different transmission device in units of packets. The first interface selects signals having the same destination from the signals contained in the received frame and stores the selected signals having the same destination in one packet.
    Type: Application
    Filed: October 22, 2009
    Publication date: May 6, 2010
    Inventors: Masatoshi SHIBASAKI, Takao Fukushima, Toshiyuki Atsumi, Yoshio Nogi
  • Publication number: 20090028548
    Abstract: The present invention provides a network at a low cost with a reduced number of components and simple management among networks anticipated to become more and more complicated, the network being capable of quick pass change upon service addition/change and failure occurrence. Namely, the present invention realizes a network configuration unnecessary for replacement of interface panels upon pass change, by using a multi-rate compatible interface panel capable of freely changing a signal type to be processed, under control of an upper level operation.
    Type: Application
    Filed: March 7, 2008
    Publication date: January 29, 2009
    Inventors: Yukihisa Tamura, Manabu Makino, Koji Takatori, Hiromi Murakami, Joshimasa Kusano, Toshiyuki Atsumi, Masatoshi Shibasaki
  • Publication number: 20090022059
    Abstract: An optical signal connection apparatus for connecting first and second optical signal transmission lines to first and second routers, respectively, is disclosed. The first and second routers are configured to handle both optical signals and electrical signals. The optical signal connection apparatus comprises a first node and a second node.
    Type: Application
    Filed: September 18, 2008
    Publication date: January 22, 2009
    Applicant: Hitachi Communication Technologies, Ltd.
    Inventors: Toshiyuki ATSUMI, Masatoshi Shibasaki, Teruhisa Takano
  • Patent number: 7433371
    Abstract: An optical signal connection apparatus includes first and second routers configured to handle optical signals and electrical signals. A first node includes a first port coupled to the first router and is configured to handle a first type of optical signals associated with the first route; a first line-setting unit configured to couple the first and second nodes for data communication between the first and second nodes; a first control unit to control setting an optical communication link between the first and second nodes; and a first signal-type storage unit. A second node includes a second port coupled to the second router and configured to handle a second type of optical signals, wherein the first information is compared with second information on the second type of optical signal to determine whether the first and second communication links are compatible to each other.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: October 7, 2008
    Assignee: Hitachi Communication Technologies, Ltd.
    Inventors: Toshiyuki Atsumi, Masatoshi Shibasaki, Teruhisa Takano
  • Publication number: 20080232818
    Abstract: A circuit capable of processing signals of different signal types is provided for identifying the signal type by the signal type setting from an administrator or by the implementation of the optical module, thereby selecting a signal processor to be used. An OTN frame standardized by ITU is used in a fixed manner independent of the signal type to be accommodated, while a corresponding SDH/SONET frame standardized by ITU is used for signal accommodation.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 25, 2008
    Inventors: Hidemasa Narita, Takao Fukushima, Masatoshi Shibasaki, Toshiyuki Atsumi, Yukihisa Tamura
  • Publication number: 20080225882
    Abstract: A transmission apparatus for multiplexing optical signals has a multi-rate signal processing unit that has a plurality of signal processing circuits in advance according to various signal speeds and frame formats and selects a necessary signal processing circuit as necessary. In addition, the transmission apparatus acquires a type code, used to identify the type of the signal of a removable optical module, from the optical module and, from the acquired information, automatically determines the operation mode of the multi-rate signal processing unit, bandwidth allocations according to the signal speeds, and monitoring item contents for different frame formats to eliminate the need for maintenance engineer's work that is otherwise required when a low-speed signal is added.
    Type: Application
    Filed: February 8, 2008
    Publication date: September 18, 2008
    Inventors: Toshiyuki ATSUMI, Masatoshi Shibasaki, Koji Takatori, Yukihisa Tamura
  • Publication number: 20080145065
    Abstract: A unit timing signal synchronized with a high-order transmission frame is used for measuring a difference between the number of data pieces of a client signal mapped to the high-frequency frame and the number of data pieces of the output client signal by integrating the difference therebetween for each unit timing signal. Then stuffing and de-stuffing operations are performed so that a integration result is zero.
    Type: Application
    Filed: May 29, 2007
    Publication date: June 19, 2008
    Inventors: Kenji Kawamura, Takashi Funada, Masatoshi Shibasaki, Yoshimasa Kusano, Yusuke Honda, Hiromi Murakami