Patents by Inventor Masatoshi Shinagawa

Masatoshi Shinagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8552549
    Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Masatoshi Shinagawa, Takeshi Kawabata
  • Publication number: 20120161313
    Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.
    Type: Application
    Filed: February 24, 2012
    Publication date: June 28, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: MASATOSHI SHINAGAWA, TAKESHI KAWABATA
  • Patent number: 8148810
    Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: April 3, 2012
    Assignee: Panasonic Corporation
    Inventors: Masatoshi Shinagawa, Takeshi Kawabata
  • Patent number: 7768138
    Abstract: In a semiconductor device, a semiconductor chip is connected to a board through an interconnection layer. A plurality of first terminals, a plurality of second terminals and a plurality of third terminals are provided on the board, the interconnection layer and the semiconductor chip, respectively. The second terminals are connected to the first terminals through the board. The third terminals are connected to the second terminals. The interconnection layer is rotatable about a rotation axis perpendicular to an upper surface of the interconnection layer. A first terminal having a specific function out of the first terminals and a third terminal having the specific function out of the third terminals are connected to each other by rotating the interconnection layer.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventor: Masatoshi Shinagawa
  • Publication number: 20100084761
    Abstract: A semiconductor device includes a mounting substrate, a plurality of semiconductor chips mounted on the mounting substrate, and a heat-dissipation area formed above the plurality of semiconductor chips. A distance between one of the plurality of semiconductor chips which generates a greatest amount of heat and the heat-dissipation area is smaller than a distance between the other semiconductor chips and the heat-dissipation area.
    Type: Application
    Filed: August 10, 2009
    Publication date: April 8, 2010
    Inventor: Masatoshi Shinagawa
  • Publication number: 20090261465
    Abstract: A semiconductor device includes a substrate having a substrate wiring, a semiconductor chip provided on the substrate, a first electrical conductor electrically connecting the semiconductor chip and the substrate wiring, and an electrically conductive pad provided on the substrate. The semiconductor device further includes a wiring member electrically connected to the electrically conductive pad and serving as a wiring path different from the substrate wiring.
    Type: Application
    Filed: March 26, 2009
    Publication date: October 22, 2009
    Inventor: Masatoshi SHINAGAWA
  • Publication number: 20090101896
    Abstract: In a semiconductor device, a semiconductor chip is connected to a board through an interconnection layer. A plurality of first terminals, a plurality of second terminals and a plurality of third terminals are provided on the board, the interconnection layer and the semiconductor chip, respectively. The second terminals are connected to the first terminals through the board. The third terminals are connected to the second terminals. The interconnection layer is rotatable about a rotation axis perpendicular to an upper surface of the interconnection layer. A first terminal having a specific function out of the first terminals and a third terminal having the specific function out of the third terminals are connected to each other by rotating the interconnection layer.
    Type: Application
    Filed: September 17, 2008
    Publication date: April 23, 2009
    Inventor: Masatoshi SHINAGAWA
  • Patent number: 7443028
    Abstract: An imaging module is formed by stacking: a first resin board; a second resin board having a first opening; a first electrically-conductive member electrically connecting the first resin board and the second resin board to each other; a printed circuit board having a second opening; a second electrically-conductive member electrically connecting the second resin board and the printed circuit board to each other; an imaging semiconductor chip mounted on the lower surface of the second resin board to cover the first opening and provided with an imaging sensor, an optical member placed on the upper surface of the second resin board to cover the first opening; a first semiconductor control chip provided with a control device for controlling operation of the imaging sensor and mounted on the lower surface of the first resin board.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 28, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Motoaki Satou, Takeshi Kawabata, Masatoshi Shinagawa, Toshiyuki Fukuda
  • Publication number: 20070138619
    Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.
    Type: Application
    Filed: October 25, 2006
    Publication date: June 21, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masatoshi Shinagawa, Takeshi Kawabata
  • Publication number: 20060202318
    Abstract: An imaging module is formed by stacking: a first resin board; a second resin board having a first opening; a first electrically-conductive member electrically connecting the first resin board and the second resin board to each other; a printed circuit board having a second opening; a second electrically-conductive member electrically connecting the second resin board and the printed circuit board to each other; an imaging semiconductor chip mounted on the lower surface of the second resin board to cover the first opening and provided with an imaging sensor, an optical member placed on the upper surface of the second resin board to cover the first opening; a first semiconductor control chip provided with a control device for controlling operation of the imaging sensor and mounted on the lower surface of the first resin board.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 14, 2006
    Inventors: Motoaki Satou, Takeshi Kawabata, Masatoshi Shinagawa, Toshiyuki Fukuda
  • Publication number: 20060118934
    Abstract: A multi-level semiconductor module according to the present invention is formed by alternately stacking resin boards and sheet members. Each of the resin boards is provided with a semiconductor device. The module includes: a rigid plate provided on one of the sheet members located at the top and having a heat dissipation efficiency higher than those of the resin boards and the sheet members; and a through buried conductor penetrating the resin boards and the sheet members and being in contact with the rigid plate.
    Type: Application
    Filed: October 20, 2005
    Publication date: June 8, 2006
    Inventors: Takahito Ishikawa, Motoaki Satou, Toshiyuki Fukuda, Takeshi Kawabata, Masatoshi Shinagawa
  • Patent number: 7035751
    Abstract: To provide a nonvolatile memory microcomputer with which a step of testing a microcomputer unit using a logic tester can be omitted, thereby reducing the testing cost. A memory tester supplies test data and expectation data to the nonvolatile memory microcomputer, and the nonvolatile memory microcomputer stores them in a nonvolatile memory. Subsequently, upon receiving an address signal, the nonvolatile memory outputs a test signal and an expectation signal based on test data and expectation data corresponding to the address signal. The test signal is supplied to a circuit block in the microcomputer unit, to drive the circuit block. The circuit block returns a test result signal, which is output to the memory tester together with the expectation signal. The memory tester compares the test result signal and the expectation signal, to judge whether the microcomputer unit operates correctly.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 25, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masatoshi Shinagawa, Akifumi Kawahara, Tetsuyuki Fukushima, Masakazu Kurata, Manabu Komiya
  • Publication number: 20040153924
    Abstract: To provide a nonvolatile memory microcomputer with which a step of testing a microcomputer unit using a logic tester can be omitted, thereby reducing the testing cost. A memory tester supplies test data and expectation data to the nonvolatile memory microcomputer, and the nonvolatile memory microcomputer stores them in a nonvolatile memory. Subsequently, upon receiving an address signal, the nonvolatile memory outputs a test signal and an expectation signal based on test data and expectation data corresponding to the address signal. The test signal is supplied to a circuit block in the microcomputer unit, to drive the circuit block. The circuit block returns a test result signal, which is output to the memory tester together with the expectation signal. The memory tester compares the test result signal and the expectation signal, to judge whether the microcomputer unit operates correctly.
    Type: Application
    Filed: October 28, 2003
    Publication date: August 5, 2004
    Inventors: Masatoshi Shinagawa, Akifumi Kawahara, Tetsuyuki Fukushima, Masakazu Kurata, Manabu Komiya
  • Patent number: 5463831
    Abstract: It is an object of the present invention to provide such a weather strip that a noise is prevented from being caused as a window pane is moved up and down in contact with the strip. The weather strip 9 according to the present invention includes a base portion 11, a seal lip 12, and a seal portion 14 having an internal opening 13. The pane contact part 20 of the seal portion 14 is made larger in thickness than the pane non-contact part 21 thereof. The pane contact part 20 is bent at the bent portion 20a thereof. The surface R of the bent portion 20a, with which the window pane 8 comes into contact, is a curved surface nearly unchanged in radius of curvature. The strip 9 has a first groove 22 inside a first bend point 18, and a second groove 23 inside a second bend point 19. The second groove 23 is larger in depth but smaller in width than the first groove 22.
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: November 7, 1995
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masatoshi Shinagawa, Hideyuki Hashimoto