Abstract: An apparatus stores path configuration information specifying a first path configuration and a second path information each of which indicates a target path configuration from a target processor to IO devices. When an error is detected from among the IO devices in a state where the target path configuration is the first path configuration, the apparatus changes the first path configuration to the second path configuration. When an error is detected from among the IO devices under the second path configuration, the apparatus identifies a suspect component included in the target path configuration, based on a comparison result of comparison between a first IO device whose error has been detected under the first path configuration, and a second IO device whose error has been detected under the second path configuration.

Abstract: An apparatus stores path configuration information specifying a first path configuration and a second path information each of which indicates a target path configuration from a target processor to IO devices. When an error is detected from among the IO devices in a state where the target path configuration is the first path configuration, the apparatus changes the first path configuration to the second path configuration. When an error is detected from among the IO devices under the second path configuration, the apparatus identifies a suspect component included in the target path configuration, based on a comparison result of comparison between a first IO device whose error has been detected under the first path configuration, and a second IO device whose error has been detected under the second path configuration.

Abstract: An information processing apparatus includes a processor, a first memory, and a second memory, wherein the second memory includes a first data storage region having a first data capacity and a second data storage region having a second data capacity smaller than the first data capacity, and the processor is configured to, in a case of executing first processing, select the first data storage region as a storage region for data to be written into the second memory by the first processing, and select the second data storage region as a storage region for data to be written into the second memory by second processing, and in a case of not executing the first processing, select the first data storage region as a storage region for data to be written from the first memory to the second memory by the second processing.

Abstract: An information processing apparatus includes a processor, a first memory, and a second memory, wherein the second memory includes a first data storage region having a first data capacity and a second data storage region having a second data capacity smaller than the first data capacity, and the processor is configured to, in a case of executing first processing, select the first data storage region as a storage region for data to be written into the second memory by the first processing, and select the second data storage region as a storage region for data to be written into the second memory by second processing, and in a case of not executing the first processing, select the first data storage region as a storage region for data to be written from the first memory to the second memory by the second processing.

Abstract: A memory control method and a memory control device each suitable for information processing systems such as multiprocessing systems where plural data processing systems concurrently execute an operating process, and more particularly a memory control method and a memory control device each of which controls the data holding state of a buffer memory unit arranged in each of data processing units on a store-in basis to gain high speed access to the main storage unit. The memory control device issues a predetermined process command to be sent to the buffer memory unit in the data processing unit, and sets a flag showing a process under request, to a portion to be processed by the predetermined process command in a tag copying unit in the memory control device. Information regarding whether a block including a process request address exists in the buffer memory unit and whether the block is being processed currently are simultaneously obtained by retrieving only the tag copying unit.